Other Parts Discussed in Thread: LMX2582
Hello E2E Team,
I am using ADC ADC12DJ3200 in my module.
I am giving 3.2GHz Clock signal through LMX2582 RFPLL as same as EVM.
I am getting NSD of -150.8 dBFs/Hz instead of datasheet value -151.8 dBFs when no input is given.
Noise Floor of LMX2582 is -156dBC/Hz at 3.2GHz as per datasheet which is less than ADC NSD.
When I am giving -1dBFs input power and input frequency 4997MHz, I got NSD of -141.6 dBFs/Hz and SNR of 49.6 dBFs
Datasheet SNR is 52.6dBFs at 4997MHz.
What is the reason for this noise floor degradation from -150.8 to -141.6 dBFs/Hz.? Is this because of clock or something else? Which parameter of Clock will reduce the NSD of ADC?
How to calculate that noise floor degradation theoretically? Please suggest any app notes (if any)
Thanks,
Sakthi
