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ADS1263: Clarifying design consideration

Steven Park
Prodigy 60 points
Part Number: ADS1263

Hello,

I am writing a library for the ADC circuit and wanted to clarify if I understood the datasheet correctly. There are three questions in different aspects of the chip.

1. Correlation between Data Rate, Sinc Filter, and conversion latency

I think I understand that the data rate is determined by the clock frequency and the decimation of the first and second digital filters. I am a little confused about the Data rate from 14400 to 38400 SPS. When I select these sampling rates by changing DR[3:0], does the second filter gets bypassed internally to meet the sampling rate, regardless of FILTER[2:0] bits? And does this also mean the conversion latency becomes only SINC5 amount listed in tables 9-13 in the datasheet? 

After the first conversion with the latency provided by table 9-13, it says the subsequent conversion occurs at a nominal data rate. Does this mean, for example at 38400SPS, the first conversion happens 0.207ms but the next conversion is going to happen at 1/38400, in continuous conversion mode?

2. When CRC bits are set to enable either CRC or Checksum, does this introduce any delay in conversion or data transmission compare to when it's disabled ?

Thanks,

Steven

  • 0
    TI__Mastermind 35241 points

    Hi Steven Park,

    Most of these questions are answered in our application note on Conversion Latency: https://www.ti.com/lit/sbaa535. Please review this information and let me know if you have any additional questions.

    The CRC does not impact the conversion latency in that it does not impact the digital filtering. There are more bits to provide to the ADC (on DIN) and clock out of the ADC (on DOUT), so this requires additional SCLKs. There is also some time for your controller to calculate the correct CRC value. However, this times should be insignificant to the overall conversion delay because they are relative to the SCLK speed.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 60 points

    Hi Bryan,

    Thanks for suggesting the application note on Conversion Latency. The application note answered most of my questions as you mentioned in your reply. However, my question regarding the configuration of the digital filter setting and data rate is not answered yet.

    On page 43 of the datasheet (I wasn't able to attach image), the digital filter block diagram shows 1st and 2nd stage filter before the filter output. I would like to configure the setting so that I only use the first stage filter (sinc5) to achieve the maximum datarate of 38400SPS. However, the filter register bit in MODE1 register doesn't have an option for not selecting the second stage filter. It only have filter from sinc1 to FIR. Does this mean that the ADC will disregard the second stage filter when the DR bits in MODE2 are set to 1111?

    -Steven

  • 0 in reply to Steven Park
    TI__Mastermind 35241 points

    Hi Steven Park,

    Correct, selecting a data rate of 38 kSPS negates the selection of the filter bits in the MODE1 register. In other words, selecting 38 kSPS automatically selects the SINC5 filter, and the filter bits are effectively don't care.

    If you then only changed the DR bits in the MODE2 register to say 1200 SPS for example, whatever values were programmed into the FILTER bits would take effect.

    -Bryan