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ADS8166 sampling problem

Other Parts Discussed in Thread: ADS8166, ADS8168EVM-PDK

hello team,

       I use ADS8166 to convert 8 channels(From AIN0 to AIN7 auto sequence mode), and I find if  just AIN0 is added on some voltage(2.048V)  , after converting, we can see AIN0 is 32768, AIN1 is also with some value, nearly 100,  but AIN2 is nearly 0.

      And also , I do another test;  just AIN1 is added on some voltage(2.048V),  we can find AIN2 has some value, AIN3 is nearly 0.

     And so on......

     So, I guess the continuous 2 conversions, the 2nd convert shall be influenced by the 1st convert ? 

     So, if you have some experience about it ? 

     Pls give me some advices,  thanks a lot!

BR

  • Hello,

    I am almost certain that this is a settling time issue.  The input sampling capacitor does not fully settle when changing from a channel at 2.048V and then to the next channel sitting at 0V.  If this is the case, you can slow down the sample rate to 50% to prove that this is the root cause.  You may need to adjust input filter values, or possibly use a higher speed input amplifier to eliminate this problem.

    If you could share a screenshot of the schematic including the ADS8166 and the input RC values and any input amplifiers, I can provide some better suggestions on how to improve performance.

    1. What is the desired sample rate for the system?

    2. What is an acceptable error?  100 codes is probably much too high; is 10 codes acceptable, or something less than the noise floor?

    You can also refer to the ADS8168EVM-PDK Users Guide (higher speed version of ADS8166) for an example circuit that supports data rates up to 1MSPS.

    https://www.ti.com/lit/ug/sbau291/sbau291.pdf

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Thanks!

    input filter is R = 470R , C = 100nF

    1. how to slow down the sample rate to 50%, in ADS8166,  250k-sps is fixed?  or setting by certain register?

    2. acceptable error is nearly 10.

    3. in our system, we trig 14 channels in every 1 microsecond,  4us is cycle time.

  • Hello,

    Thanks for the additional information.

     1. how to slow down the sample rate to 50%, in ADS8166,  250k-sps is fixed?  or setting by certain register?

    The sample rate is controlled by the frequency of the chip select (/CS) pin.  In order to sample at the maximum rate of 250ksps, then the frequency of the /CS pin would be 250kHz.  As a test, reduce the frequency of the /CS pin by 50%.  This should reduce the error.

    What is the frequency for the /CS signal?

    2. acceptable error is nearly 10.  Based on your R,C values and error to less than 10 counts, you can sample up to 8ksps total, or scan through 14 channels in 1.75 millisecond.  Changing C from 100nF to 10nF, you can sample up to 40ksps with less than 10 counts of error, or up to 28ksps with less than 1 count of settling error for full 16b performance.

    3. in our system, we trig 14 channels in every 1 microsecond,  4us is cycle time.  I do not understand this statement.  The ADS8166 would require at least 56us (microseconds) to scan 14 channels. 

    Do you scan 14 channels in 1 millisecond (0.001 seconds)?  This would equate to a sample rate (/CS frequency) of 14ksps.

    Based on your input R,C filter values, this is a settling time issue.  You can reduce errors by reducing the /CS frequency (ADC sample rate), or by reducing the input filter values.  If your sample rate (/CS frequency) is 14ksps, reducing your C value to 10nF should eliminate all crosstalk error due to settling time.

    Regards,
    Keith

  • Thanks for your kindly reply!

  • You are welcome!