• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 152 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC09QJ1300-Q1: ADC application questions

Bryce Xun
Mastermind 18160 points
Part Number: ADC09QJ1300-Q1
Other Parts Discussed in Thread: LMK00304, TPS22917

Hi expert,

I am new to ADC devices, and the customer has several questions about the device application, please kindly find below questions,

1. The output pins of ADC09xJ1300: D8+, D8-... What are the usage of these pins? How to distinguish the four channels of A,B,C,D, does the result of these channels output in turn?

2. The customer wants to use the following reference design, can the 50MHz VCXO be removed and use the internal VXCO of FPGA?

3. From the Figure B-3 above, can LMK00304 be removed? What does this do? What is the function of the other pins-SYNC, SYSREF, PLLREF0? What signals are required from the FPGA?

4. From the picture below, does the TPS22917 is a must if Y2 is always working?

5. How does the Tdiode+/- work when the temperature is over target?

Thank you for your reply.

Best regards,

Bryce

  • 0
    TI__Mastermind 20541 points

    Hi Bryce,

    1. The output pins of ADC09xJ1300: D8+, D8-... What are the usage of these pins? How to distinguish the four channels of A,B,C,D, does the result of these channels output in turn?

    Pins D0+,D0-....D7+,D7- are high speed Serdes lanes. The output data from the ADC is sent on these lanes based JMODE selection. Each JMODE has transport layer table in datasheet table 8-21 to table 8-36 which describes how data is packed from different channels on different lanes. 

    2. The customer wants to use the following reference design, can the 50MHz VCXO be removed and use the internal VXCO of FPGA?

    Does the customer wants to use the ADC PLL ? If yes, I would recommend to use EXT REF to ADC PLL option instead. 

    3. The SYNC pin is used to JESD handshake process for 8b/10b modes between the FPGA and ADC. The sysref signal can be used achieve deterministic latency. PLLREFO is copy the clock signal which was provided to ADC PLL as a reference. Only the signal signal is required from the FPGA. The other signals are routed from the ADC to FPGA. The sysref signal can come from the FPGA or can be proved with external clock generator. 

    4. The Y2 is powered with the load switch if load switch is removed the Y2 will not get powered on. 

    5. Tdiode+- is a diode located inside the ADC chip. it is only meant to read the temperature from the ADC. 

    Regards,

    Neeraj