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DAC38J84: Configured vs Received JESD204B parameter

Part Number: DAC38J84

I'd like to verify that the JESD204B parameters have been received correctly during the ILAS sequence. The datasheet is unclear on which registers are RO and which are RW, so I'm not sure if they represent the received data, or the register written configuration.

Is there a way to verify which JESD204B link parameters have been received during the ILAS sequence?

  • Hi,

    If the ILAS sequence check is not matched between the JESD204 TX and JESD204 RX link, then the link configuration error will persist and cannot be cleared

  • Thank you for responding Kang. Just so I'm clear: All the parameters from the other registers are the "expected" (host writes to these registers directly), and then checking bit 13 shows whether the expected vs received was a match?

  • Hi

    All the parameters from the other registers are the "expected" (host writes to these registers directly)

    Please clarify your definition for other registers. I would say most of the registers are written by the host directly. There are alarm registers which requires the host to read back the status of the JESD204 state machine or other DAC functionalities.

    6064.DAC3xJ8x ILA Sequence.xlsx

    You can check the above spreadsheet for ILAS sequence detail.

    By the way, the ILAS sequence is the least used alarm in the industry. This is a simple check from the host side to ensure the DAC side is programmed correctly on the LMFS setting. It is like a teacher making sure the student is attending the class, and calling out their names and expect a "present" is responded.

    Most of the folks in the industry simply ignore this alarm due to the complexity of programming on both FPGA and DAC side. On the DAC side, this can be done by setting sync_request_ena to 0xDF and error_report_ena to 0xDF (to not include link configuration error).

    6663.DAC3xJ8x JESD204B Sync Request and Error Report.pptx