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ADS8904B: Missing information in the datasheet and unable to read registers from ADC

David Marty
Intellectual 635 points
Part Number: ADS8904B

Hi!

The ADC is configured with these values in the registers:
    PD_CNTL = 0x00
    SDI_CNTL = 0x00 (default SDI mode)
    SDO_CNTL = 0x0F (external SCLK, SDR, Data are output on SDO[0..3], SDO follow the source-synchronous protocol)
    DATA_CNTL = 0x00 (parity disabled)
    PATN_LSB = 0x00
    PATN_MID = 0x00
    PATN_MSB = 0x00

We observed that if the parity isn't enabled, the ADC returns only 20 bits which isn't explain in the datasheet.

We also tried to reread the registers without success, the ADC read command isn't explain, what are we supposed to do after sending the RD_REG command ?
We tried:
    maintain the CS low and send clock pulses : wrong value read
    release and reactivate the CS and send clock pulses : wrong value read

Thanks for your help

Best regards

  • 0
    TI__Guru**** 171226 points

    Hi David,

    Sorry for the confusion here!  When the parity bits are disabled, you are mostly correct - you get the 20-bit data followed by 2 zeros.  Figure 43 and 44 shows the parity computation unit appends the parity to bits 1 and 0.  Just below Figure 44, you should see that when parity is disabled, the D[1] and D[0] bits are set to 0.  For the register read functionality, please take a look at Table 2 on page 27.  You need to follow the RD_REG (B[21:17] = 10001) command with the 9=bit address of the register you want to verify followed by 8 trailing zeros.  From section 7.5.1, the register detail is located in the D[21:14] in the next frame followed by zeros loaded in bits D[13:0].

    If you are not seeing this behavior on your end, please let us know what you are seeing.  If you can capture details on a logic analyzer, that would be helpful too!