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ADC12DJ3200: Input Full Scale on the AD12DJ3200(JMODE16) xilinx FPGA Chipscope

LIM HJ
Prodigy 50 points
Part Number: ADC12DJ3200

I want to know the digital value of Input Full Scale on the AD12DJ3200(JMODE16) xilinx FPGA Chipscope.

Please check if there is anything missing in ADC setting or getting digital value.

1. Device: AD12DJ3200

   - JMODE 16 (Dual channel setting, but only B-Channel is used, Complex I, Q)

   - FS_Range_A, FS_Range_B Register : 0x2000 (about 500mVpp)

   - JESD204B connection -no Scramble - Data format: 2's Complement

   - Disable Gain Boost

2. FPGA: xilinx xcku060

   - Using JESD204 IP

   - To check ADC Input Full Level through ChipScope (Digital value)

   - Input Waveform : Sine Wave Adjust the ADC input level (RF input) to around 500mVpp based on the ADC Datasheet,

     check the I and Q outputs of each 16bit in JMODE16 Since the LSB of 16bit is OVR_T, exclude it and add '0' (I[15:1] & '0', Q[15:1] & '0') to become Signed 16bit Value range of Signed 16bit is +32767 ~ -32768,

     about +32000 ~ -32000 should be output when Full Scale Level is entered. However, in actual output, about half of the values are output.

Thank you!

Best Regards.

  • 0
    TI__Mastermind 22590 points

    Hi Lim,

    For the ADC, are you using the 5200RF EVM or your own board design?

    Thx,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 50 points

    I am using my own design. However, in order to verify the contents, the same test was performed using ADC12DJ3200EVM, but the result was the same as that of our own design.

  • 0 in reply to LIM HJ
    TI__Mastermind 22590 points

    Hi Lim,

    Both devices, have a 1Vpp fullscale input capability. So this would be expected.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 50 points

    I understand what you are saying. However, this is when I use the input full scale as 500mVpp.

    After setting the input full scale of the ADC to 0x2000 and checking 500mVpp using an oscilloscope at SG, the SG signal was input to the ADC.
    In this case, it seems correct that the value output through the xilinx Chip Scope should be output near the full scale value of -32768 ~ +32767, but it was confirmed that it was actually output at about 1/2 of it.

    When set to full scale with 1Vpp, the value output on xilinx FPGA ChipScope can be checked as 1/2 at the same input (500mVpp).

  • 0 in reply to LIM HJ
    TI__Mastermind 22590 points

    Hi Lim,

    Can you please clarify? When you are measuring with the oscilloscope, you are probing at the analog input pin of the ADC?

    If so, keep in mind the analog input is differential, so for a 1Vpp fullscale (default). Each analog input pin (AIN+ and AIN-) will be swinging +/-250mVpp.

    Is that what you are measuring?

    Also, what is SG mean?

    Regards,

    Rob