Other Parts Discussed in Thread: ADC12J4000, LMK04828, , TRF3765
HELLO,
I AM USING ADC12J4000 BOARD AND INTERFACING IT WITH ZC706 BOARD.
I AM USING JESD204B IP AS A RECEIVER RUNNING IN 8,8,8 MODE. THESE ARE THE SET PARAMETERS
FS = 3000MHZ DDR BYPASS MODE
K = 4
LANE RATE ( RECEIVER SIDE) = 6000M
REF CLK = 150M AND SYS CLOCK = 75MHZ (64BIT OUTPUT I.E., 6000/80 = 75M)
THE QPLL IS GETTING LOCKED AND THE SUBCLASS 1 MODE IS ALSO WORKING AND THE SAMPLE DATA IS ALSO RECEIVED. BUT THE DATA IS NOT THE ACUTUAL SAMPLE VALUE. EVEN WHEN I TRIED THE RAMP MODE OR SHORT TRANSPORT MODE THE VALUES ARE NOT CORRECT.
I AM UNABLE TO DEBUG THE PROBLEM. HELP ME TO SOLVE THE ISSUE.
NOTE: THE POLARITY REVERSAL OF THE RX_LANE OUTPUTS ARE ALSO TAKEN CARE.