• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 46 subscribers
  • Views 160 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J4000EVM: RECEIVING CORRUPTED SAMPLES DATA IN THE JESD RECEIVER

RAJESH VARMA
Prodigy 20 points
Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12J4000, LMK04828, , TRF3765

HELLO,

I AM USING ADC12J4000 BOARD AND INTERFACING IT WITH ZC706 BOARD.

I AM USING JESD204B IP AS A RECEIVER RUNNING IN 8,8,8 MODE. THESE ARE THE SET PARAMETERS

FS = 3000MHZ DDR BYPASS MODE

K = 4

LANE RATE ( RECEIVER SIDE) = 6000M

REF CLK  = 150M AND SYS CLOCK =  75MHZ (64BIT OUTPUT I.E., 6000/80 = 75M)

THE QPLL IS GETTING LOCKED AND THE SUBCLASS 1 MODE IS ALSO WORKING AND THE SAMPLE DATA IS ALSO RECEIVED. BUT THE DATA IS NOT THE ACUTUAL SAMPLE VALUE. EVEN WHEN I TRIED THE RAMP MODE OR SHORT TRANSPORT MODE THE VALUES ARE NOT CORRECT.

I AM UNABLE TO DEBUG THE PROBLEM. HELP ME TO SOLVE THE ISSUE.

NOTE: THE POLARITY REVERSAL OF THE RX_LANE OUTPUTS ARE ALSO TAKEN CARE.

  • 0
    TI__Guru* 91947 points

    Rajesh,

    Is your IP using both a reference clock and core clock? See the attached example which is using the same hardware setup as yours except for the TSW14J10EVM. Notice the settings for the LMK04828 on the ADC12J4000EVM. Are you setting these correctly? The attached ini file shows the JESD parameters used by the ZC706. The firmware for this project can be downloaded from the TSW14J10EVM product folder on the TI website.

    Regards,

    Jim

    ADC12J4000_BYPASS_ZC706.iniADC12J4000_bypass_ZC706.pptx

  • 0 in reply to jim s
    Prodigy 20 points

    there is only reference clock input in my IP. I am not using TSW board, but directly connecting the adc to the zc706. The reference clock frequency input is also being generated internally in fpga. I initially used the refrence clock inputs for IP from the FMC HPC (given by adc DEVCLKARX pins). But I am unable to set the required frquency in that pins by the register values. when 3000GSPS is used for example. what is the frequency inputting to LMK04828 for which we can add the DIV values in the registers to get our required frequencies??

  • 0 in reply to jim s
    Prodigy 20 points

    And the IP iam using is TI204C

  • 0 in reply to RAJESH VARMA
    Prodigy 20 points

    LMK = is it every time FS/2??

  • 0 in reply to RAJESH VARMA
    TI__Guru* 91947 points

    Rajesh,

    Are you using the TRF3765 to clock the ADC? This is the default clock for the ADC on the EVM. Can you send the register settings by saving the config file using the low level view tab?

    What do you mean by LMK = FS/2???

    To set DEVCLKARX = 150MHz, do the following writes in the low level tab in the LMK04828 section:

    Address   Data

    0x110      0x0A

    0x116      0xF0

    0x117     0x11

    For FPGA SYSREF = 75MHz, do the following writes:

    0x10F    0x10

    0x10C   0x20

    0x10E   0xF0

    0x10B   0x01

    0x139   0x03

    0x13A   0x0

    0x13B   0x14

    0x143   0x10

    Regards,

    Jim