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ADC3221EVM: Not working with TSW1400, "Clock from ADC EVM is not received by TSW board"

Yuan Dao
Prodigy 110 points
Part Number: ADC3221EVM
Other Parts Discussed in Thread: ADC3221, CDCE6214, LMK03806, LMK03318

TSW reports "Clock from ADC EVM is not received by TSW board":

USER_LED2 is on. Both EVMs are in default condition.

  • 0
    TI__Genius 11261 points

    Hi Yuan,

    Can you please send a picture of your setup? What are you using as a clocking source?

    It would be helpful if you could also provide the current draw that you see from both the ADC3221EVM and the TSW1400EVM. 

    Regards, Amy

  • 0 in reply to Amy
    Prodigy 110 points

    I don't have a signal generator, so J9 is not connected. That is the problem, right?

    Does any of the two EVM can provide such a clock? Can TSW1400EVM generate such clock signal?

  • +1 in reply to Yuan Dao
    TI__Genius 11261 points

    Hi Yuan,

    Yes, if you do not have a clocking signal connected to J9, then this is the source of the error. 

    In general, we do not recommend using an FPGA as a clocking source. FPGAs have poor jitter performance that will severely degrade the quality of the ADC performance. TI recommends a high quality signal generator (such as an SMA100A or SMA100B), or you could consider a clocking chip EVM that meets the ADC jitter requirement from our clocking product line: https://www.ti.com/clocks-timing/generators/products.html 

    Regards, Amy

  • 0 in reply to Amy
    Prodigy 110 points

    What is ADC jitter requirement? From the list, some clock generator has 100 ps peak to peak jitter, are those acceptable? 

    Which clocking product do you recommend for ADC clock?

    Thank you.

  • 0 in reply to Yuan Dao
    TI__Genius 11261 points

    Hi Yuan,

    The ADC jitter requirement can be found on page 47 of the datasheet (8.3.2.2 SNR and Clock Jitter). If you look at Figure 8-7, you can see how SNR degrades over input frequency due to external clock jitter. If you want the device to perform in line with the given specifications in the datasheet, a low jitter clock is required. A high quality signal generator such as an SMA100A has a jitter spec on the order of femtoseconds (fs). 

    Regards, Amy

  • 0 in reply to Amy
    Prodigy 110 points

    Thank you. For the purpose of low-jitter ADC clock input only, can you recommend a clock generator IC with jitter around or less than 1000 fs, have short lead-time and cost-efficient?

  • 0 in reply to Yuan Dao
    TI__Genius 9885 points

    Hello Yuan,

    What is your sample rate/clock frequency? How many outputs do you need from the clock (i.e, do you only have one ADC to sample or more than one? Does anything else in your system require a clock?)? If you require several outputs, what other frequencies does the clock need to generate? Thanks!

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 110 points

    Thank you. I will use only one ADC3221, sampling rate at 25 MHz.

    Other than ADC, a MCU need a clock, although MCU can use external crystal, it's preferable if MCU also source from the same low-jitter-clock for better synchronization. The MCU accept external clock source from 16 MHz to 40 MHz, so the same 25 MHz frequency should suffice. Can both MCU and ADC source from a single clock output, or is it better to use two clock outputs at the same frequency? 

  • +1 in reply to Yuan Dao
    TI__Genius 9885 points

    Hello Yuan,

    Based on your requests, it looks like the CDCE6214 is the best solution for your requests. It has the capability to output synchronized outputs for 2 25-MHz outputs. It should also meet your jitter and cost-efficient requirements. I have added the clocks team to this thread to ensure a short-lead time.

    Also, if you want optimal jitter performance, I would recommend to also look into LMK03806 and LMK03318, which are two of our better performing parts. Hope this helps!

    Best,

    Andrea

  • 0
    TI__Prodigy 200 points

    Hi,

    Can I please know the project timelines here? This will help me recommend best solution. Seems like system needs two output clock gen? 

    Thanks,
    Kumarpal. 

  • 0 in reply to Kumarpal Mandoth
    Prodigy 110 points

    Prototyping now, production in a year. Why would project timeline affect chip recommendation?

    Can two chips (ADC, MCU) share the same output of a clock generator?

    Thank you.

  • 0 in reply to Yuan Dao
    TI__Genius 11261 points

    Hi Yuan,

    I sent you an E2E friend request. 

    Please direct message me and provide a good email contact to discuss clocking options. I will connect you with our clocking team directly.

    Amy

  • 0 in reply to Yuan Dao
    TI__Prodigy 200 points

    I will respond now directly on our email thread , the one that Amy created.