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ADC12DJ3200: Ramp test mode

Part Number: ADC12DJ3200

Hi team,

One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions

ADC set to JMODE1 mode, lane_rate=6.4G ,K=4 , jesd204B_core lck=160MHz, sysref is both 20MHz, using a sampling frequency of 3.2GHz.

The following is the ADC configuration sequence, configured in order:

0:dout<=24'h0000B0; ///***///进行软复位

delay of 100ms 

1: dout<=24'h020000; ///***///清除 JESD_EN (始终在 CAL_EN 之前)
2: dout<=24'h006100; ///***///清除 CAL_EN (始终位于 JESD_EN 之后)


3:dout<=24'h000200;
4:dout<=24'h001000;
5:dout<=24'h002300;
6:dout<=24'h002970;
7:dout<=24'h002A00;
8:dout<=24'h0030C4;
9:dout<=24'h0031A4;
10:dout<=24'h0032C4;
11:dout<=24'h0033A4;
12:dout<=24'h003800;
13:dout<=24'h003B00;
14:dout<=24'h004803; ////// 将串行器预加重设置为3
15:dout<=24'h006001;
//14:dout<=24'h006101;
16:dout<=24'h006201;
17:dout<=24'h006400;
18:dout<=24'h006B00;
//18:dout<=24'h006C01;
19:dout<=24'h007000;
20:dout<=24'h007100;
21:dout<=24'h007980;
22:dout<=24'h007A00;
23:dout<=24'h007B00;
24:dout<=24'h007C00;
25:dout<=24'h008000;
26:dout<=24'h008100;
27:dout<=24'h008200;
28:dout<=24'h008300;
29:dout<=24'h008400;
30:dout<=24'h008500;
31:dout<=24'h008600;
32:dout<=24'h008700;
33:dout<=24'h008800;
34:dout<=24'h008900;
35:dout<=24'h008AFF;
36:dout<=24'h008B07;
37:dout<=24'h008CFF;
38:dout<=24'h008D07;
39:dout<=24'h008EFF;
40:dout<=24'h008F07;
41:dout<=24'h0090FF;
42:dout<=24'h009107;
43:dout<=24'h0092FF;
44:dout<=24'h009307;
45:dout<=24'h0094FF;
46:dout<=24'h009507;
47:dout<=24'h010280;
48:dout<=24'h010380;
49:dout<=24'h011280;
50:dout<=24'h011380;
51:dout<=24'h012280;
52:dout<=24'h012380;
53:dout<=24'h013280;
54:dout<=24'h013380;
55:dout<=24'h014280;
56:dout<=24'h014380;
57:dout<=24'h015280;
58:dout<=24'h015380;
59:dout<=24'h016000;
//60:dout<=24'h020001; //Clear JESD_EN (always before CAL_EN) Set JESD_EN (always after CAL_EN)
61:dout<=24'h020101; //Set JMODE1 ////// 设置 JMODE1
62:dout<=24'h020203; //0x202 0x03:Set KM1=3 so K=4 //////设置 KM1=3、因此 K=4
63:dout<=24'h020301;
64:dout<=24'h020401; //Use SYNCSE input, offset binary data, scrambler enabled 输出数据的格式: ////// 使用 SYNCSE 输入、偏移二进制数据、启用扰频器
65:dout<=24'h020504; //
66:dout<=24'h020600;
67:dout<=24'h020700;
68:dout<=24'h020800;
69:dout<=24'h020900;
70:dout<=24'h020C00;
71:dout<=24'h020D00;
72:dout<=24'h021000;
73:dout<=24'h0211F2;
74:dout<=24'h0212AB;
75:dout<=24'h021307; //Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples //////启用超范围,将超范围保持设置为最大周期8*2^7=1024个样本
76:dout<=24'h021400;
77:dout<=24'h021500;
78:dout<=24'h021602;
79:dout<=24'h021700;
80:dout<=24'h021800;
81:dout<=24'h021902;
82:dout<=24'h022000;
83:dout<=24'h022100;
84:dout<=24'h022200;
85:dout<=24'h0223C0;
86:dout<=24'h022400;
87:dout<=24'h022500;
88:dout<=24'h022800;
89:dout<=24'h022900;
90:dout<=24'h022A00;
91:dout<=24'h022BC0;
92:dout<=24'h022C00;
93:dout<=24'h022D00;
94:dout<=24'h023000;
95:dout<=24'h023100;
96:dout<=24'h023200;
97:dout<=24'h0233C0;
98:dout<=24'h023400;
99:dout<=24'h023500;
100:dout<=24'h023400;
101:dout<=24'h023500;
102:dout<=24'h023800;
103:dout<=24'h023900;
104:dout<=24'h023A00;
105:dout<=24'h023BC0;
106:dout<=24'h023C00;
107:dout<=24'h023D00;
108:dout<=24'h024000;
109:dout<=24'h024100;
110:dout<=24'h024200;
111:dout<=24'h0243C0;
112:dout<=24'h024400;
113:dout<=24'h024500;
114:dout<=24'h024800;
115:dout<=24'h024900;
116:dout<=24'h024A00;
117:dout<=24'h024BC0;
118:dout<=24'h024C00;
119:dout<=24'h024D00;
120:dout<=24'h025000;
121:dout<=24'h025100;
122:dout<=24'h025200;
123:dout<=24'h0253C0;
124:dout<=24'h025400;
125:dout<=24'h025500;
126:dout<=24'h025800;
127:dout<=24'h025900;
128:dout<=24'h025A00;
129:dout<=24'h025BC0;
130:dout<=24'h025C00;
131:dout<=24'h025D00;
132:dout<=24'h02B000;
133:dout<=24'h02B105;
134:dout<=24'h02B500;
135:dout<=24'h02B600;
136:dout<=24'h02B700;
//137:dout<=24'h02C11F;
138:dout<=24'h02C23F;
139: dout<=24'h006101; ///***///设置 CAL_EN (始终在 JESD_EN 之前)
140: dout<=24'h020001; ///***///设置 JESD_EN (始终在 CAL_EN 之后)
141: dout<=24'h006C00; ///***///将 CAL_SOFT_TRIG 设置为低电平以复位校准状态机
142: dout<=24'h006C01; ///***///将 CAL_SOFT_TRIG 设置为高电平以启用校准

Read the latest status of the register:

0208:7c

02C1:1f

When using Ramp test mode, the output of both IP cores (out_data[255:0] and out_data_2[255:0]) is always the same, as shown in the figure:

The gt0_rxdata[32:0]、gt1_rxdata[32:0]、gt2_rxdata[32:0] of the two IP cores are almost the same, as shown in the figure:

The parsed sampling data appears to be the same for every 8 sampling points, as shown in the figure:

What could be the reason for this phenomenon? Could you please provide some troubleshooting suggestions?

Best Regards,

Amy Luo

  • Hi Amy,

    In the octet ramp pattern mode, the behavior will be as follows: each lane will count from 

    • If F*K < 256, it will count from 0x00 to (F*K)-1
    • If F*K > 256, it will count from 0x00 to 0xFF and wrap around and resume from 0x00 until the end of the multi-frame

    In JMODE1 F = 8 and you are programming K = 4, that is the reason why each lane is counting from 0 to (8*4)-1 = 0 to 31.

    if you want each lane to count from 0 to 255 program, K = 32 and each lane should count from 0 to 255.

    Regards,

    Neeraj

  • Hi Neeraj,

    Glad to see your reply.

    The customer's issue has been resolved. Thank you.