Hi team
I am sending ADC sampled analog data to my FPGA. I am able to reconstruct the signal at my FPGA. But when i look for the Bit error rate(BER) in the data it is on the high side. Note that my CDR is also locked while eye diagram is also good enough. Any clues on why BER on the high side though CDR is locked and eye opening is also good enough.
-trs
