ADS7056: Current sense with precision of units of mA and capability of > 60A range?

Hi Emmanuel,

Great questions!  The parts you are looking at span several different teams here at TI.  You landed in the data converter forum so lets start with the ADS7056.

1.  The REF1933 actually has dual outputs which are often used as the ADC reference and then a common mode point for an INA type circuit.  The REF3033 has better accuracy, but you also need 50mV of headroom, so you would need a little more than the 3.3V shown on your schematic, or use the REF1930/REF3030 with 3.0V powering the ADS7056.  The ADS7056 can operate up to 2.5MSPS, but the INA's won't be able to drive the input running at that speed.  Is that what you want to do in the end?

2.  Whichever REF option you choose in the end, I suspect you will be (or at least trying to be) simultaneously sampling all three phase currents?  That is going to put 3x the transient load on one device versus sampling the three phases in turn.  Check the load transient plots in the REF33xx and REF19xx datasheets.

3/4.  See 1 above, you won't be able to settle the analog inputs running the ADS7053 at 2.5 MSPS.

5.  Lets address 1-4 and go from there.

Hello, Tom

Thanks for your help! I have some questions:

You went directly to the point: why INA won't be able to drive the input running at that speed?

Hi Emanuel,

We have a neat little tool in our Analog Engineer's Calculator that addresses the drive needs for Successive Approximation Register converters.  The ADS7053 has a minimum acquisition time of 95nS and uses a 16pF capacitor for the sample/hold circuit.  Plugging those numbers into the calculator tool provides the following:

To run the ADS7053 at full speed, you need a buffer with nearly 50 MHz of bandwidth.  The INA293 has about 1.3MHz bandwidth which could support running the ADS7053 around 300kSPS.  You could put a faster buffer between the INA and the ADC, but you still have to deal with the settling time of the INA.

Tom, 

For the INA240, the settling time is around 10us. So, the real throughput with a buffer of 50MHz BW would be around 100kSPS?

If it's true, what do you suggest to get a better data rate of at least 1MSPS?

Hi Emanuel,

You can still sample the output of the INA @ 1MSPS, you will get points throughout its settling time.  The high speed buffer on the input to the ADS7053 will let you accurately capture samples on the input to the ADC.  If there is ringing through the settling time of the INA, you should be able to accurately follow that.

Hi Tom,
I understand.
About the REF3033: You're right, I would sample the three phases at the same time. In order to do that, what do you recommend to solve the load transient fluctuation? Or is this something to mitigate?

Hi Emanuel,

I like the idea of one reference for all three phases, you could add a buffer to help get through the transients.

Hello, Tom.
If adding a buffer to the REF3033, wouldn't it introduce a noise to the system?
What PN you suggest in order do this properly?

Hi Emanuel,

We have a series of videos on driving the reference of SAR converters that you might find useful.  Start here https://www.ti.com/video/series/analog-to-digital-converters-adcs.html and scroll down the page to the topic "Driving the reference input on a SAR ADC".

Hi, Tom.
Thanks for sharing this!
Another thing... should I power ADS7056IRUGR's pins 4 and 6 with REF3033 output? Would it be desirable, considering it could probably result in voltage ringing from the digital circuitry of the ADS7056IRUGR?

Hi Emanuel,

DVDD is the noisier digital side of the chip, if you can keep the analog clean with the REF3033 and provide the digital from a different source, that would be the preferred solution.

Hi Tom,
Thanks again.
I've been thinking about doing some modifications in my previous design based on your notes:



Consider the schematic bellow. This is repeated three times in the schematic.
For the AVREF, see the schematic below:



I have considered using one ref3033 for each half-bridge. Then I've thought about putting a buffered voltage reference (REF6230).
Look at the transiente response for the REF6230:

It looks good for this application as the three ADS @ 2MSPS would get arount 2.5mA max, in my view.
In this context, does all this make sense to you?
(I suggest you to make some notes about this, please) 

Hi Emanuel,

This looks good to me!  Thank you for the update!

Hi Tom,
Could you tell what would be the bit error for 2.5mV for each ADS?
(would it be less than 1 bit?)

Hi Emanuel,

The ADS7056 is a 14-bit ADC.  With 3.0V reference (your AVDD supply), the LSB size is ~183uV.  Your 2.5mV error would represent about 13.6 LSB's.

Hi Tom,
I think I didn't express myself correctly (or I did not understand your answer). I explain:
Considering a variation in the VREF of around 2.5mV, in case the three ADS being sampled together, how it would impact in the LSB error for its input? Could you tell an aproximation for this error? 

Hi Tom,
Due to some limitations in our project, I have some questions:
1. Is it possible to use the ADS7057 instead of using the ADS7056? Could we change the PN wihout any modifications? What modifications are needed, otherwise?

2.  As show below, instead of using the REF6230 we decided to substitute it for a REF3033 buffered with an OPA357. Is that a good solution?

Hi Emanuel,

The ADS7057 and ADS7056 are pin-to-pin compatible, but the ADS7057 has a fully differential input stage where the ADS7056 is single ended.  You might be able to put VIN(-) to vref/2.

Hey Tom,
1. Is there any problem on putting the ADS7057 VIN(-) pin to "vref" instead of "vref/2" ? What about putting this VIN(-) pin to GND?
2. Could you please give me feedback about the question 2, about the REF3033 buffered with an OPA357?

Sorry Emanuel, I didn't mean to hit the 'reply' button just yet. 

With the ADS7057, you could tie AINm to GND, but either way you will loose half the input range.  Look over Table 1 in the ADS7056 and Table 2 in the ADS7057 datasheets.  The ADS7056 has a straight binary output with VINp from 0-Vref while VINm is at ground (output code 0x0000 to 0x3FFF).  The ADS7057 would give you 0x0000 to 0x1FFF under the same conditions.  The buffer with REF3033 should be fine!

No problem about the reply!
Well, for INA241A1 zero current means output voltage at vref/2.
So, using the ADS7057 with AINM = 1.65, for zero current: AINP - AINM = 1.65 - 1.65 = 0.
for max positive current: AINP - AINM = 3.3 - 1.65 = 1.65.
for max negative current: AINP - AINM = 0 - 1.65 = -1.65.
So in my conclusion, for full scale operation, both pins 6 (AVDD) and 8 (AINM) of the ADS7057 should be connected to vref/2 = 1.65v, is that right?

Yep!  If you bias both inputs to the Vcm level of the ADS7057, your zero current should give you 0x0000 output.

Hey Tom, 

I forgot to ask... How the opa as a buffer would improve BW of the Ina241A2, for example? Could you show a simulation to measure the 3db cutoff frequency of the cascaded Ina241a2 with the opa in buffer configuration? 

Hi Emanuel,

The OPA as a buffer is not going to impact the bandwidth of the INA directly.  However it will provide a faster response to the sample and hold of the ADC.  Assuming that there is no transient or large scale step response settling on the INA ahead of the buffer at the instance of ADS7095 sampling, the OPA should be able to settle the analog input to the ADC to within 1/2 LSB during the acquisition stage.  No promises, but I'll see what I can do to get a TINA-TI or PSPICE for TI model together for you - that will take a little time.

Hi Tom, 
I've changed a bit my schematic, which I show below:



Considering this schematic, my question is: are both R75 and R63 needed?
What would be the impact on the functionality of the ADS if these resistores were removed and the capacitor were put to GND?
Removing these res would create any offset or lose bit resolution?

Best Regards, Tom.

Hi Emanuel,

Give me a day to go over your changes, I'll try to get back to you by this time tomorrow!

Hi Tom,
Ok, I will be looking at this.

Also, check if the unity-gain configuration for the OPA looks right, or if the analog line has any downside, if possible.

Thanks again for your attention!

Hi Emanuel,

Gain looks OK, I don't really see any other issues.  If you can leave the series R through a proto type stage and populate them with zero ohms, that would be ideal.  Gives you the chance to see the overall impact in the end with and without.

Hi Tom,
The PGA113 would be fine to support the 2MSPS of the ADS? How the signal integrity would be impacted?

Hi Emanuel,

I believe you'll be OK - how much gain are you planning on implementing with the PGA? 

The max gain would be 10 or 20. Is that good?
My concern is about the ADS to drain a considerable current due to high sampling rate and this distorch the signal from the PGA.

At a gain of 20V/V, you should have better than 1MHz bandwidth so I don't see an issue there.  With the buffer between the PGA and ADC, I don't think you'll have any issues.