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Original question:
Hello,
Now we have the board, and the board has been verified including the clock generation with LMK04828 and FPGA
We are now trying to get the JESD204B working between ADC32J25 and FPGA.
We are leveraging a previously working FPGA design with JESD204B.
The 1st step is to see if we can receive a test pattern from ADC32J25.
Attached is the ADC register configuration.
Would you be able to take a look at the configuration?
Regards,
Andrew
Hello Andrew,
I'm not sure what exactly you would like for me to check from your configuration. When I loaded it to the GUI, I was able to obtain a capture, meaning the ADC is outputting data (picture below where I have my analog input operating at 25-MHz and 10dBm).
Also, 5516.ADC3xJxx_128MSPS_Operation_LMK_Setting.cfg is the default config file in case that's what you were looking for. You can load it by clicking on the "Low Level Vi" tab, and then the "Load Config" button.
If you could also write you set up the GUI to do, that would be very helpful as well.
Thanks,
Andrea
Hi Andrea,
We are following the write format described on pg 55 of the datasheet
So the "0" corresponds to the fact that A14 should be "1".
Thank you,
Andrew
Hi Andrea,
We are still troubleshooting.
In order to have a better visibility, we would like to see if we can detect a test pattern.
Could you take a look at the screenshot and see if the test pattern generation is configured correctly?
Also included is the config file. Would it be possible for you to load the config file into your setup for verification?
Thank you for support.
Andrew
Hello Andrew,
Could you take a look at the screenshot and see if the test pattern generation is configured correctly?
By just looking at the screenshot, the GUI should be setup correctly for that page. I set my GUI up the same way for that page and I obtained a capture showing the pattern toggling (from the Codes window; however, from the Real FFT window I saw nothing):
Here is my config with a working system (both LMK04828 and ADC32J25).
TestPattern_Toggle_ADC32J25.cfg
Also included is the config file. Would it be possible for you to load the config file into your setup for verification?
When I loaded the config file into my setup, the ADC was not picking up a clock, and hence, I was not able to obtain a capture. This means your configuration for the LMK04828 is incorrect since the part is not able to lock the PLL (when LED D4 is lit, it means the LMK04828 PLL is locked). If you tell me what frequencies you would like to output, if you have a set input frequency, and if there are any other requirements (such as SYSREF, etc) that you need from the LMK04828, I can help create a config with the correct LMK04828 setup.
Also, note that you don't need to check the "Align Test Pattern" option to output a test pattern. You only need to check that box if you need to align the outputs of the test patterns across the different channels. Hope this helps and let me know if you need anything else from me.
Good Luck,
Andrea
Andrew,
0xBCBC indeed refers to K28.5 characters and shows that the ADC is in CGS stage of bring-up sequence. See below image.
Can you add SYNC to the ILA IP block and also trigger your ILA on SYNC de-assertion (rising edge of SYNC) and verify that data changes from 0xBCBC to K28.0 character and Dx.y data symbols? 4 multi-frames after the SYNC de-assertion the actual ADC data will be present at the FPGA if the ADC has exited ILAS (initial lane alignment sequence).
What is the rx_tvalid signal in your ILA?
Thanks, Chase
