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ADC12DJ5200RFEVM: Question about Dual channel work mode and onboard clock

Lei Zhou
Prodigy 100 points
Part Number: ADC12DJ5200RFEVM
Other Parts Discussed in Thread: LMX2594, LMK04828

Hi,

I have questions about the dual channel work mode and onboard clock.

1. The max sample frequency of onboard clock is 10.4GHz/single channel & 5.2GHz/dual channel? I have looked through the user guide and datasheet, it seems LMX2594 is powerful enough to provide 5.2GHz sample clock,  but there is not an exact answer.

2. If the dual channel work mode is selected, what should I do? If there exists some user guide  to which i can refer(We have TSW14J57). And the dual channel are synchronized? 

Thanks

  • 0
    TI__Expert 4070 points

    Hello Lei,

    1. The ADC in single channel mode is capable of 10.4 GSPS because it is interleaving the two ADC's on the device. In dual channel mode the ADC is only capable of 5.2 GSPS. I am little confused what you mean by "LMX2594 is powerful enough" can you elaborate on this please. 

    2. Also there is an evm user guide that will walk you through how to setup and use the TSW14j57 board here is a link to it.

    https://www.ti.com/lit/ug/slau640b/slau640b.pdf?ts=1690232094567&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FADC12DJ5200RFEVM

    If you have any other questions please let me know.

    Best,

    Eric Kleckner

  • 0 in reply to Eric Kleckner
    Prodigy 100 points

    Dear Eric Kleckner,

    Thanks for your answer!

    For my orignal question 1, I have the question whether the onboard clock can support the max sample frequency. So, I looked through the user guide & ADC datasheet,  and found the LMX2594 generate the sample clock as shown in fig. 1. Next, I looked through the datasheet of LMX2594, and found its an application which use 100MHz Fosc to generate 8GHz Fout as shown in fig. 2. Therefore, the Fosc in fig.1 (EVM) is 260MHz, it should have the ability to generate a 5.2GHz clock. That's the reason i say "LMX2594 is powerful enough". But I'm a layman in electronic circuit, i have to look for expert's advice. Slight smile

    For your response 2, I had looked through the evm user guide, and successfully sampled the data in single-channel. However, there is no information about how to set for dual-channel in the guide. If there is  some pdf about dual-channel that can be referenced?

     

    Best

    Lei Zhou

     

    fig.1 onboard clocking system block diagram

    fig.2 

  • +1 in reply to Lei Zhou
    TI__Expert 4070 points

    Hi Lei,

    Yes the adc12dj5200EVM can sample at max frequency when using the onboard clock, what happens is both adc cores are given a 5.2 GHz sample clock and then those ADC's are interleaved effectively doubling your Fs. This feature is only available in single channel mode. 

    To set dual or single channel mode you have to pick the right JMODE, I have included a screenshot from the ADC's user guide that describes each JMODE and their features. A simple example would be JMODE 1 you would want to use this JMODE if you wanted to run the ADC at its max sampling frequency on one channel. Then if you wanted a dual channel ADC you could pick JMODE 2 for instance.

    Hope this helps, let me know if you have any other questions.

    Best,

    Eric Kleckner

  • 0 in reply to Eric Kleckner
    Prodigy 100 points

    Dear Eric Kleckner,

    Your reply helps me a lot! 

    I still have a little question.  Supposing that  a common external reference clock(260MHz) is provided to two EVM boards, does this mean that the sampling clocks of the two boards are synchronized? 

    Thank you very much!

    Best

    Lei Zhou

  • +1 in reply to Lei Zhou
    TI__Expert 4070 points

    Hi Lei,

    For external reference clocking if you provide a common external reference this will not make the two evm boards synchronized. To do so you must do following...

    • Ensure that the LMX2594 on both evms are synchronized. Although this is not explicitly a feature of the device gui it can be accomplished by writing directly to the LMX's registers in the "Low Level" tab of the gui. Once you do this both the sampling clocks will be synced.
    • Ensure that the LMK04828 on both evm are synchronized, similar to LMX it is not a feature of the device gui but can be accomplished by writing to the registers. Now the FPGA clk and FPGA sys ref will be synced.
    • If you are using multiple FPGAs you need to ensure that there is a sync signal between them so they capture data at the same time.

    After meeting these criteria then the two EVM boards will be synchronized.

    Best,

    Eric Kleckner 

  • 0 in reply to Eric Kleckner
    Prodigy 100 points

    Dear Eric Kleckner,

    Thank you very much for your detailed answer!

    Best

    Lei Zhou