ADC12DJ3200EVM: JESD Elastic Buffer Overflow/Underflow

Nicholas Strong

Prodigy 90 points

Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200

Good afternoon,

We had a design with the Xilinx JESD IP using the ADC12DJ3200 that was working correctly.

We did not test it for a week or so and the next time we turned it on the GTH_RXBUFSTATUS signal was varying wildly.

Sometimes it was showing elastic buffer overflow, elastic buffer underflow, etc, etc.

Like this:

What could be the cause of these issues?

What information can I provide that may help debug this issue?

over 1 year ago

0 Neeraj Gill over 1 year ago

TI__Mastermind 20541 points

There are few possible reason which would cause this issue.

1. Sysref frequency being used is not correct.

2. The GTH clock to the FPGA is has drifted too much from the correct frequency.

3. The GTH_RXBUFSTATUS depth is not enough to absorb the delay variation from all the serdes lanes.

Regards,

Neeraj

+1 Nicholas Strong over 1 year ago in reply to Neeraj Gill

Prodigy 90 points

Hey Neeraj,

Thank you for your answer.

So, we discovered the cause of the issue, which was that one of the power lines to the ADC had an issue. Once this was resolved the ADCs synced and transmitted data correctly and the JESD received them correctly.

Could you perhaps help me to understand why this would cause the issue?

0 Neeraj Gill over 1 year ago in reply to Nicholas Strong

TI__Mastermind 20541 points

Hi Nicholas,

Which power line has the issue. Can you please elaborate into that?

Regards,

Neeraj

0 Nicholas Strong over 1 year ago in reply to Neeraj Gill

Prodigy 90 points

Looks like it was the VA11 line.

0 Neeraj Gill over 1 year ago in reply to Nicholas Strong

TI__Mastermind 20541 points

Hi Nicholas,

VA11 is the main analog supply. That is reason you were able to get ADC working.

Regards,

Neeraj

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ADC12DJ3200EVM: JESD Elastic Buffer Overflow/Underflow