ADS8528: tcclk and BUSY signal about ADS8528

haifei wang

Part Number: ADS8528

Hi All,

I am using the ADS8528. In my design I have tied the CONVST of ABCD channels together.

From the description in section 9.3.1.6, it says the BUSY output transitions low for a single conversion clock cycle(tcclk) whenever a pair completes a conversion.

(1) What's the value of tcclk? Is it 67ns which defined in tBUFS ?

(2) When CONVST of ABCD channels is tied together, will the BUSY output transitions low for four conversion clock cycles(4* tcclk) or still one conversion clock cycles(1*tcclk)?

9 months ago

0 haifei wang 9 months ago

Prodigy 20 points

I mean in section 9.3.1.6 of the datasheet.

0 haifei wang 9 months ago

Prodigy 20 points

I mean in section 9.3.1.6 of the datasheet.

0 haifei wang 9 months ago

Prodigy 20 points

I mean in section 9.3.1.6 of the datasheet.

0 Tom Hendrick 9 months ago

TI__Guru**** 170495 points

Hi Haifei,

Section 9.3.1.6 of the ADS8528 applies to staggered or sequential application of the four CONVST signals. Above you mentioned that the four CONVST signals are tied together. In that case there would not be any transition of BUSY - it would be a single pulse similar to what is shown in Figure 35. The TCCLK is the conversion clock, which can either be internal or external. The internal conversion clock of the ADS8538 is 1.33uS (see section 7.6).

0 haifei wang 9 months ago in reply to Tom Hendrick

Prodigy 20 points

Hi Tom,

Thanks for your answer. I understand now only one pulse will be generated if we tied 4 CONVST together. But for the TCCLK, does the 1.33us means the Conversion time instead of the TCCLK when using the internal conversion clock? I guess it is 67ns which defined in section 7.9 for tBUFS?

0 Tom Hendrick 9 months ago in reply to haifei wang

TI__Guru**** 170495 points

From section 7.9, the conversion time is 19-20 tcck cycles. With the 1.33uS conversion time, you can see that relates to an internal clock of ~15MHz. The tBUFS parameter is one clock cycle which accounts the the one clock uncertainty in the conversion clock cycles. Reason being there is now way to exactly synchronize the CONVSTs to the internal conversion clock. When using an external conversion clock, your CONVST input can be synchronous to your CCLK, so the tBUFS can be 0.

+1 haifei wang 9 months ago in reply to Tom Hendrick

Prodigy 20 points

I am clear now, Thank you very much Tom.

Data converters

Data converters forum

ADS8528: tcclk and BUSY signal about ADS8528