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ADS9218: design issue

Rhea Gao
Expert 2290 points
Part Number: ADS9218

Hi，

I have customer who use this chip and have some design issues.

1. Whether this chip can be input with differential clock?  Differential is available on the EVM, but it is not written in the datasheet.

...

2. What does DNP mean on EVM?

3. How does SYNC work? The manual gives less information.

Many thanks~

  • 0
    TI__Guru 59136 points

    Hello Rhea,

    Thank you for your post.

    Yes, the ADS9218 can accept a differential LVDS clock or a single-ended CMOS clock input. The DNP ("do not populate") resistor between SMPL_CLKP and SMPL_CLKM is for terminating the differential clock input, if needed. By default, the EVM is configured for a CMOS clock input, so the termination is not installed and SMPL_CLKM is shorted to GND through a shunt.

    The data sheet the customer is using is preliminary. We are working on the complete data sheet now with more information. Our systems team can provide more details shortly.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Expert 2290 points

    Hi Ryan，

    OK ，thanks~

  • 0 in reply to Rhea Gao
    TI__Expert 3715 points

    Hi Rhea,

    The SYNC input on the ADS9218 device family allows synchronization of the over-sampling (averaging) filters in the ADC. A pulse on the SYNC pin resets the over-sampling filter (if enabled) in the ADC - this way all ADCs in the system start averaging at the same sampling clock edge after the SYNC pulse.

    If there is only 1 ADS9218 in the system or synchronization across multiple ADS9218s is not required or over-sampling feature of ADS9218 is not used, the SYNC pin can be connected to GND.

    Regards,
    Rahul