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ADC3424: Serial interface spec

Taku Murayama
Intellectual 990 points
Part Number: ADC3424

Could you tell me the serial interface spec of ADC3424?

 

According to ADC3421-24.pdf P48 Table6,

fSCLK = 20MHz MAX

tDSU = 25ns min

tDH = 25ns min

 

But, when fSCLK = 20MHz, this clock time (tSCLK) = 50ns,

and if 50% duty, clock high time = 25ns, clock low time = 25ns.

 

Then, tDSU and tDH can't meet 25ns min.

(Bacause it is impossible to get longer tDSU/tDH than clock high/low time.)

 

Does this spec indicate we can't operate this interface with 20MHz frequency?

 

Thank you.

  • 0
    TI__Mastermind 19505 points

    Hi Taku,

    Yes, a 20MHz SPI is the max possible serial interface rate for this device. If operating at 20MHz with an EXACT 50% duty cycle, in order for it to work at all, in theory you will have to have a SPI driver capable of setup and hold at a minimum of 25ns. The entire time when the SCLK is low, the driver MUST have data ready to be clocked. The entire time the SCLK is high, the driver must hold the data. This means an instantaneous transition of data is required. Is this achievable in reality? For most customers, no. Some customers have transition rates in the ps range, which is when a 20MHz spi would be used for this device. The reality is that this specification in the datasheet for setup and hold time is higher than what the device actually needs to function. Instead of 25ns setup and hold time, picture it as 24.5ns setup and hold times.

    If the application can tolerate a slower serial interface speed, then I highly suggest to reduce this for a much easier to use design. Considering this is a very basic device, there will not be hundreds or thousands of registers to program, so increasing the SPI speed to 20MHz and the challenges that ensue when doing so is a tremendous trade off as far as applied effort level versus returned results for a few tens of register writes.

    Regards, Chase