ADS1298: Raising the SPI to a higher frequency will not read any information

Hi Cherry,

May I ask who might be this customer? if not allow to disclose in public, please convert this to internal or send me an email.

I don't recognize and not familiar with ESP32S3, so I don't have knowledge to help anything related to ESP32S3.

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Regarding to SPI for ADS1298, customer needs to make sure the timing follow and meet the datasheet page 17 

7.6 Timing Requirements: Serial Interface

7.7 Switching Characteristics: Serial Interface

e.g.

if 2.7V<=DVDD<=3.6V, TSCLK or SCLK frequency have to be slower than 20 MHz

if 1.65V<=DVDD<=2V, TSCLK or SCLK frequency have to be slower than 15.01 MHz

and 

make sure to use SPI settings "NOTE: SPI settings are CPOL = 0 and CPHA = 1."

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May I ask what data rate(SPS) do they plan to use?

and up to which SCLK frequency do they start seeing unable to read?

Also,

Make sure - 

"(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission."

and

"As seen in Figure 63, the DRDY output goes high when conversions are started and goes low when data are ready"

So, please check does the host/master's SPI always wait at least 7 SCLK falling edges after START command, and wait for the /DRDY goes low to read?

In other words, they may want to use scope probes to compare digital signals timings to compare between

when SPI read works properly

and

when they start seeing SPI not working properly,

and check&find whether any timing misalign? 

Thanks

Hi,

Thank you for the support!

The timing of the SPI protocol is only CS falling and arrives at the same time as one edge of SCLK, without reaching the minimum 17-ns delay. The customer need to achieve 8 ksps sampling rate on them, so the clock rate to read SPI is around 8 MHz, using the rising edge of /DRDY to read data. Is it possible?

Also, could you help recommend a register configuration which requiring a data sample rate of 8Ksps and a fall detect is an AC detect?

Thanks and Regards,

Cherry

Hi,

To set the output data rate, need to ask customer what mode is customer using?

CONFIG1: Configuration Register 1

High-resolution or low-power mode?

This bit determines whether the device runs in low-power or high-resolution mode. 0 = LP mode 1 = HR mode

For High-Resolution mode, fMOD = fCLK / 4. For low power mode, fMOD = fCLK / 8

then, based on the above mode selection, they can set the output data rate DR[2:0]

001: fMOD / 32 (HR Mode: 16 kSPS, LP Mode: 8 kSPS)

or

010: fMOD / 64 (HR Mode: 8 kSPS, LP Mode: 4 kSPS)

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are they referring to the AC lead off detection?

They need to set the following -

LOFF: Lead-Off Control Register (address = 04h)

FLEAD_OFF[1:0] set to 01 = AC lead-off detection at fDR / 4

And,

"The ac excitation signals are introduced at a frequency that is above the band of interest, generating an out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of the excitation signal at the output spectrum, the lead-off status is calculated"

Customer will need to do post DSP and algorithms when using AC lead off detection.

Thanks