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ADS127L01EVM: Enquiry about the pin status of DRDY during SPI DOUT active phase

Ernest Yong
Expert 4315 points
Part Number: ADS127L01EVM

Hi Team,

May I know if it the pin DRDY toggling during the SPI DOUT active (Data transfer phase) is consider normal? (pls look at the pic attached below) Or there are something wrong with this fenomena?

Thank you for your time. 

Best Regards,

Ernest

  • 0
    TI__Mastermind 43000 points

    Hello Ernest,

    No, this is not correct behavior.  Looking at the DRDY signal, it appears that the ADC data rate is the default 512ksps.  The SCLK needs to be running at a much higher frequency, or, a lower data rate needs to be used.

    When /DRDY goes low, the data (24b or 32b) needs to be clocked out of the device before the next /DRDY low, or in the above example, in less than 1.9us.  With 24b data, this will require an SCLK frequency minimum of 13.3MHz, and for best performance, SCLK should equal the main CLK frequency of 16.384MHz in this case.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Expert 4315 points

    Hi Keith,

    Thanks for your quick response. 

    By the way, the ADC date rate we set is 8ksps and SCLK is 2MHz. I think there are some miss information with the pic attached in previous post.

    Here I attach a new one for you. So our side here just wondering why the DRDY is toggling during the data transfer via DOUT.

    Best Regards,

    Ernest

  • 0 in reply to Ernest Yong
    TI__Mastermind 43000 points

    Hello Ernest,

    O.K. now I understand the image.  DRDY goes high on the first SCLK falling edge, which appears to be correct in the latest image.  However, it should not toggle after it goes high during SCLK activity.  Either the logic probe is picking up noise due to poor ground connection, or there is a lot of noise on the /DRDY line coupled from the SCLK which is causing the logic analyzer to show erroneous DRDY activity.

    I suggest looking at DRDY with a scope probe to get a better idea, but I think your logic analyzer is simply picking up noise from SCLK and incorrectly showing activity on DRDY.

    Regards,
    Keith