ADS1248: Problem determining DRDY status from the DOUT/DRDY pin

Chris hl93

Part Number: ADS1248

I am finding that the DOUT/DRDY line stays at the level of the LSB of the previous transfer for a length of time that varies depending on the data rate. For instance, when running 2000 SPS DR, I need to delay 1026 us before I can use DOUT/DRDY to determine data ready condition, whereas for a 5 SPS DR, I need to wait 409601 us. Additionally, the period from the falling edge on the actual DRDY pin to the next falling edge varies from about 500 us when the previous transfer clocked out FFFFFF and about 541 us when the previous transfer clocked out a write to the MUX0 register.

This design will use the ADS1248 to digitize and transfer the data for 4 inputs through a 4-line isolator which passes DIN, DOUT/DRDY, SCLK and /CS. START and /RESET are tied high and the modulator CLK pin is tied low. The actual DRDY pin is floating, though I am monitoring it with a scope. My FPGA sends an initialization sequence of 4003080030494A0008FF (80 clocks) after the appropriate power up delay to enable DRDY mode, set the data rate, MUX, PGA, etc., and I have verified that the registers are being written properly. This initialization leaves the converter in the RDATAC mode. Upon DOUT/DRDY going low, it sends 24 1 us period clocks to shift out either 400008 or FFFFFF (for my current test), and receive the results of the previous conversion. (Eventual MUX0 writes will be 4000xx to cycle between the 4 channels.)

Is the above the expected operation? Is there a better way to use the DOUT/DRDY pin to determine ready status?

TIA,

Chris

over 7 years ago

0 Joseph Wu over 7 years ago

TI__Guru* 95185 points

Chris,

First, just so that this setup is clear, let me go through your configuration sequence:

40 - WREG starting at 00
03 - Write four registers
08 - AIN1=AINP, AIN0=AINN
00 - No VBIAS lines
30 - Internal reference always on, selected
49 - PGA=16, 2000SPS
4A - WREG starting at 0A
00 - Write one register
08 - DOUT/DRDY functions as both DOUT and DRDY
FF - Dummy read/write(?)

I don't see any issues in this sequence. It should be fine for what you want to read.

As for the timing numbers you quote, the time it takes to determine the DRDY condition appear to be longer than I would expect. However, some of this may be associated with the setup and configuration. I don't think these are unexpected operation. There are two things that I think may clear up the read timing.

First, I would use 32 clocks to clock out the data. After the first 24 clocks, the last 8 clocks return the DOUT/DRDY line high so that DRDY can be seen as a transition low. This is shown in Figure 75 on page 43 of the datasheet. With this, the DOUT/DRDY should be similar to the /DRDY output in timing and it should be always visible and not dependent on the LSB of the data.

Second, the timing of the conversion is changed because of a write to the device. If you write to any of the MUX0, VBIAS, MUX1, or SYS0 registers, the device changes the configuration, and the device immediately resets the digital filter, and starts a new conversion. This restarts the clock on the conversion time. This action is described in the Digital Filter Reset Operation on page 38 of the datasheet. I think this is why some of your timing for the /DRDY is off from your expected values.

If timing is critical, I would use a external clock with good tolerance. The internal oscillator has a tolerance of about ±5%.

Hopefully this clears up your question. If it doesn't or you have other questions, feel free to post back.

Joseph Wu

0 Chris hl93 over 7 years ago in reply to Joseph Wu

Prodigy 160 points

Hello Joseph,

Thanks! I missed that information in figure 75. The extra 8 clocks fixed the issue and the converter is operating as expected.

Regards,

Chris

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ADS1248: Problem determining DRDY status from the DOUT/DRDY pin