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DAC3482: How much is minimum fDAC

Kazuhiko Hirano
Genius 12263 points
Part Number: DAC3482

Hello,

My customer would like to use DAC3482 at the following conditions.
   -  Baseband I/Q input data rate = 5.12MSPS
   -  X16 interpolation
   -  fDAC = 5.12MSPS x 16 =81.92MSPS
However, looking at Figure 37 to 45 of the datasheet, no plot data below fDAC=100MSPS.
DAC3482 does not work at 81.92MSPS?
How much is the minimum fDAC at DAC3482?

Best regards,

K.Hirano

  • 0
    TI__Guru 67824 points

    Hi Hirano-san,

    The lower limit of the Fdac will be constrained by the external clock driver and the AC coupling network from the clock driver to the DAC3482. The AC coupling network is a high pass response.

    The customer will also need to consider that the LVDS bus of their FPGA will be based on the FPGA DLL/PLL fabric, which may have a certain operational range.

  • 0 in reply to Kang Hsia
    TI__Genius 12263 points

    Kang,

    Thank you for your response.

    Do you mean if the DACCLK driver and ac-coupling circuit could pass 81.92MHz clock and the FPGA could drive 5.12MSPS LVDS I/Q data, DAC3482 itself could work at fDAC=81,92MSPS?
    Or do you think it is generally difficult to achieve 81.92MHz clock ac-coupling circuit and 5.12MSPS LVDS data from an FPGA?

    Best regards,

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Guru 67824 points

    Hello Hirano-san,

    Let's use an example. With 100nF of ac coupling capacitor and with 100ohm of the DACCLK termination, the high pass corner for the R/C network is 1/(2*PI*100*100nF) = 15.9kHz. Therefore, the clock rate of 81.92MHz clock will pass the high pass corner without any concerns.

    As long as the FPGA DLL/PLL can support the 5.12MSPS LVDS I/Q data, I also do not have concern.

    We had customers asking if we can slow down the clock to the kHz range, and therefore, I wanted to be clear on the mechanism for the lower side range of the DACCLK.

    -Kang