After reading other posts/questions about the DAC38J84 and reading through the datasheet, I still have a question about the correct values to set the registers in the DAC38J84 for JESD204B operation using:
8 JESD204B lanes total (2 sets of four JESD lanes with each set coming from a separate JESD204B PHY within an FPGA)
The functional block diagram in the datasheet shows 8 incoming JESD204 serial lanes, 4 actual DAC's, and 2 main paths from those 8 JESD204 serial lanes out to the 4 DAC's.
-In setting the LMFS in the DAC38J84, is L = 8 since I have all 8 JESD lanes connected to the FPGA JESD204 PHY's? or is L = 4 since I have 4 of the DAC38J84 JESD204 lanes (D0P/N to D3P/N) connected to one FPGA JESD204 PHY and the other 4 DAC38J84 JESD204 lanes (D4P/N to D7P/N) connected to a different PHY?
-Is M = 4 since I am making use of all 4 of the DAC's (DACA, DACB, DACC, & DACD) within the DAC38J84?
