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TLA2024: sometimes I2C read yields incorrect values

Part Number: TLA2024

The following images depict a scenario in which, after writing 0x5383 to the Configuration Register (0x01) of TLA2024 (0x48), then immediately subsequent read of that register yielded a value of 0xD3FF. There appears to be an issue in the waveform after "Read [0x48] + ACK." The enlarged view of that portion of the waveform is shown in the second image. This phenomenon is observed especially at low temperatures (around -20°C) and occurs approximately once every few hundred attempts. What is considered as a possible cause?

  • Hello,

    After looking at the digital waveform I would agree, there seems to be an unexpected start command on the I2C bus. Could you capture an oscilloscope shot of an I2C transfer on the VDD, SDA and SCL pins and monitor them for any abnormalities?

    Where are you receiving the incorrect register value of 0xD3FF? I don't see a part of the logic capture that could result in that value.

    Thanks,

    Levi DeVries

  • The attached images are captures of the waveform at the time of the observed phenomenon, obtained in both digital (upper two channels) and analog 10MS/s (lower two channels) formats.

    The portion of the waveform labeled "0xFF + Missing ACK/NAK" appears to indicate that, similar to the previous occurrence, the TLA2024 is not operating correctly beyond the first bit. While our tools decode this section as "0xFF + Missing ACK/NAK," the actual device driver reads it as 0xD3FF without detecting any errors. However, it should be noted that the lower 8 bits of this register were previously written as 0x83, not 0xFF.

    We have confirmed a similar phenomenon occurring with the SoC's I2C Hardware IP and the i2c-gpio (bitbang) included in the Linux kernel.

    I checked that the waveform obtained in analog format complies with the I2C Timing Requirements of the TLA2024 and does not appear to violate any specifications.

    The second image is an enlarged view of the "0xFF + Missing ACK/NAK" section (SCL=77kHz, pull-up=3.3V). In this portion as well, there doesn't seem to be any issue with the I2C Timing Requirements.

    Are there any other points that might potentially be causing the issue?

  • Hello,

    I would agree that this seems like unexpected behavior for the TLA2024. As I mentioned before, I'd also like to see the voltage level of VDD during the error if you could capture that as well. I would also be interested in seeing your schematics around the device pins. Are there any other devices on the I2C bus?

    Could you do an A-B-A swap of the device to determine if this is a problem with this unit in particular? You also mentioned that the problem seems to get worse at colder temperatures, you could also test the device below -20 degrees Celsius to see the the performance continues to degrade with temperature.

    Thanks,

    Levi DeVries

  • > As I mentioned before, I'd also like to see the voltage level of VDD during the error if you could capture that as well.

    The attachment is an enlarged image taken at the time of the issue occurrence. You should be able to verify the voltage and timestamp. If you see anything that appears to be a problem, please let me know.


    > I would also be interested in seeing your schematics around the device pins. Are there any other devices on the I2C bus?
    > Could you do an A-B-A swap of the device to determine if this is a problem with this unit in particular?
    > You also mentioned that the problem seems to get worse at colder temperatures, you could also test the device below -20 degrees Celsius to see the the performance continues to degrade with temperature.

    The current issue is occurring only in one unit at the moment, but I cannot be certain as there are not many available units for testing. Additionally, the minimum operating temperature for the unit is -20°C, so it cannot be lowered further. We have decided to perform an A-B-A swap in the coming weeks, and I would like to confirm these details during that process.

  • Hi Hiroki Nishimoto,

    This is a holiday week in the US, therefore we will get back to you next week with a response. Thank you for your patience

    -Bryan

  • > As I mentioned before, I'd also like to see the voltage level of VDD during the error if you could capture that as well.

    The attachment is an enlarged image taken at the time of the issue occurrence. You should be able to verify the voltage and timestamp. If you see anything that appears to be a problem, please let me know.

    I was hoping to see the voltage on the VDD pin of the device (the power supply pin) but I only see the captures for the SDA and SCL lines. Did you perhaps post the wrong image?

    We have decided to perform an A-B-A swap in the coming weeks, and I would like to confirm these details during that process.

    Let me know when you have more information to share and I will be happy to help you,

    Levi DeVries