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Original question:

ADS54J60: ADS54J60

ADS54J60: ads54j60

shambhuling d
Prodigy 80 points
Part Number: ADS54J60

Dear Amit,

   Now, we are able to capture the Pulse signal on HSDC pro with the help of  BD design project shared by you. But this is working fine for pulse (Pulse width : 20ns)  with frequency above1 MHz signals due to high value of core debug clock in ILA.

     Our requirement is to capture the low frequency  pulse  (Pulse width : 20ns) with 1 Hz to 500 Hz frequency. So, we request you to suggest the necessary changes to be done w.r.t vivado project.

   Also my team member(Mr. Darshan) needs your guidance w.r.t capturing these sample values in PL code and stream it to PS section. So, please share info/steps regarding what signals to be referred w.r.t Block Diagram/IP core and how to package all the script content in single project to generate final bit file.

   Regards,

Shambhuling D

(Manager,D&E/MS)

  • 0
    TI__Intellectual 1320 points

    Hi Shambhuling,

    The TI JESD IP infrastructure that was handed off to you consists of the RTL code and Vivado setup required for testing an operational link (and evaluation of the dataconverter). The points that you have requested for will need the following:

    1> The ILA clock cannot be slowed down because it needs to capture at the rate of the Rx clock. For wider pulses, what you need is a deeper capture buffer, which will typically exceed the RAM available on the FPGA. This will need the data to be exported to the DDR memory, which can be done by converting the rx_samples bus to an AXI protocol, and feeding the data to the DDR controller.

    2> Once the data is available in DDR / BRAM through the AXI bus system, you can then access the same using the PS.

    The modifications that you are requesting for will need to be carried out at your end, as TI unfortunately does not support the same. Once the link operation has been validated, the ILA (and tone generator) should be replaced with the necessary application logic to transition to a memory based source/sink architecture.

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 80 points

    Dear Amit,

     We understand that work has to be done by us. Even though pulse period is wide , we are only  interested in sampling during on time (approx 25 ns) of the pulse. So, as we are not interested in off time off the pulse(1sec to 4ms). This will reduce the  no. of samples in each cycle. 

      Is there any possibility in current b project, ILA trigger condition w.r t received samples can be set, so that capturing starts after the rising edge of the pulse.