DAC5688: CLKO output levels

Gal Davidi

Prodigy 30 points

Part Number: DAC5688
Other Parts Discussed in Thread: SN74LVC1G125, ,

Hi,

I want to ask what are the logic levels of the CLKO_CLK1 pin, in output mode.

Can you tell what the High and Low levels are, and whether or not it needs to be buffered when connected to FPGA input.

Thanks!

8 months ago

0 Benjamin Uhing 8 months ago

TI__Intellectual 2515 points

Hi Gal,

The CLKO_CLK1 output is at IOVDD which is 3.3V logic for the DAC5688. The need for a buffer will depend on your system design and loading current on the pin. Please be aware the CLKOUT delay relative to input CLK2 rising edge will increase with increasing loads. The TI DAC5688EVM uses a TI SN74LVC1G125 buffer on CLKOUT to ensure performance across cabling and to support various loads.

Regards,

Ben Uhing

0 Gal Davidi 8 months ago in reply to Benjamin Uhing

Prodigy 30 points

Hi Ben,

I did consider using the SN74LVC1G125 but i'm just not sure if it will support 160MHz clock (which is the max. for CLKO)

So can you tell if it will support it? if not, please recommend a buffer that does.

Thanks for your support,

Gal

0 Benjamin Uhing 7 months ago in reply to Gal Davidi

TI__Intellectual 2515 points

Gal,

I've heard back from our clocking team. They recommend the LMK1C11xx family of clock buffers for this use. We also have a buffer portfolio tool if this device doesn't quite meet your needs.

https://www.ti.com/product/LMK1C1102

https://www.ti.com/clocks-timing/buffers/overview.html

Regards,

Ben

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DAC5688: CLKO output levels