AFE881H1EVM: Issue with self‑test feature of the transmit and receive signal chains for system diagnostics in full duplex mode.

Hi Asha,

To help me understand your issue, are you writing the data before enabling HART and FULL DUPLEX mode?

If this is the case, you should enable HART and FULL DUPLEX before writing your test bytes.

Let me know if this resolves your issue,

Thanks,
Lucas

Asha,

Just to be sure, I think there are a few things to check.

First, I would say to use the assert the /RTS at the beginning of the HART frame and de-assert at the end of the frame. Don't try to assert/de-assert for each character. With that, you don't need such a large inter-byte gap. You might need about a gap of about a quarter bit-time between bytes but that's about it.

If you're using SPI mode, then I would set the following:

- There is a SDO starts as disabled and you need to enable it in the CONFIG register. Set DSDO to 0.
- Disable the UART in the CONFIG register. Set UART_DIS to 0.
- Make sure the SPI mode is set in the UBM register. Set REG_MODE to 0.
- Enable HART in the MODEM_CFG register. Set HART_EN to 1.
- Enable internal Duplex mode in the MODEM_CFG. Set DUPLEX_EXT to 0. This is for testing the writing/reading of the device.

I would check these settings. Using the EVM, I got the proper write/read from the device. I haven't had the chance to test the LEVEL, but just remember that all the LEVEL and LEVEL_SET registers are 4 bits, while the FIFOs are 5 bits. These LEVEL and LEVEL_SET values are the MSB of the FIFO levels (FIFO levels divided by two).

Joseph Wu

Asha,

We just noticed that the wording in the datasheet on the setting of the UART_DIS is unclear at best. To disable the UART, you would set UART_DIS to 1. I had written it wrong in the previous post. 

If you're using the EVM, it should be set correctly.

Joseph Wu

Hi Joseph,

I've set UART_DIS to 1 only.

Asha G

Joseph,

Loosing first 6 bytes while reading data at different threshold levels using FIFO_H2U_RD.

if threshold level set to 15 to write 30 bytes , the LEVEL field updating with hex 'C' and FIFO_H2U_RD register starts reading from 'C'.

if threshold level set to 5 to write 10 bytes , the LEVEL field updating with hex '2' and FIFO_H2U_RD register starts reading from '2'.

in both cases missing first 6 bytes written into FIFO_U2H_WR register.

Asha

Hi Joseph/Lucas,

any update on loosing first 6 bytes in a packet. waiting for your reply.

Asha

Hi Asha, 

We are approaching the holidays and there will be delays in responses until the end of the year as people take vacation. Lucas or Joe will get back asap. 

Best,

Katlynne Jones

Hi Asha,

I apologize for the delay. Are you able to plot your transmission using an oscilloscope or logic analyzer?

Can you also share the values of each of your Config and FIFO registers?
I'll see if I can replicate this on my EVM.

Thanks,
Lucas

Hi Lucas,

I can able to read data once i added 1.5bit times delay added while enqueuing data.its working fine but in datasheet it was mentioned ~1.5 tBAUDHART bit times FIFO Enqueuing Delay required for UBM and SPI Plus UART mode (Figure 7-22.) not for SPI mode(Figure 7-21.).

Asha G

Asha,

First, are you now able to read your data correctly without losing the first 6 bytes?

The enqueuing delay is generally an issue in the transmission of the HART data as the AFE device sends the HART signal. Figures 7-21 and 7-22 are for HART transmit timing, not for reading the data. I don't think you would need extra timing for getting data off of the FIFO.

If your still having trouble with losing the first 6 bytes reading data from the FIFO, Lucas suggested that you use a plot of an oscilloscope or a logic analyzer. Using one of those plots, you can see if the data coming in is properly triggering the IRQ to indicate the number of bytes going into the FIFO.

Joseph Wu