ADS1148: RDATAC mode, data interruption

Oba

Genius 16065 points

Part Number: ADS1148

Hello,

My customer has some questions for ADS1148.

Q1.

When the new conversion is done in RDATAC mode, the converted data is automatically loaded to the shift register.

If it is done during register access by PREG command, the PREG access is interrupted by this conversion.

They would like to understand mode detail about this behavior.

The below is the expected sequence of PREG command access.

If the new conversion is done in the middle of 1byte like the below, will the 1^st bit be wrongly shifted until next CS rising?

When the conversion is done during this access like the below, the returned register value is interrupted and corrupted by the conversion data.

In this case, does the 2^nd PREG command still work? Is the returned value of it valid (red one)?

And the below is another case.

In this case, the new conversion is done during PREG command issuing.

Is this PREG command still valid? Is the returned value of it valid?(red one)?

Q4.

They are considering to change to SDATAC mode because the host CPU doesn’t monitor DRDY signal.

In this case, the host CPU read the data by RDATA command.

Is it OK to think there is no risk to corrupt the conversion data even though the new conversion is done during RDATA command issuing?

Regards,

Oba

8 months ago

0 Bryan Lizon86 8 months ago

TI__Mastermind 39501 points

Hi Oba,

Due to the holiday week here in the US, please expect a response during the week of January 2. Thanks for your patience

-Bryan

0 Bryan Lizon86 8 months ago in reply to Bryan Lizon86

TI__Mastermind 39501 points

Hi Oba,

Can you please post the customer name in the Notes section of the Thread Tracking Toolkit?

-Bryan

0 Bryan Lizon86 8 months ago in reply to Bryan Lizon86

TI__Mastermind 39501 points

Hi Oba,

There is no "PREG" command in the ADS1148. So I will assume you are referring to the RREG command since you use "2xh" in your diagrams, which is the command for reading registers

If RDATAC mode is enabled, then the RDATAC command takes precedence over RREG, WREG, etc.

Therefore, if you issue any SCLKs after DRDY drops low when RDATAC mode is enabled, the ADC will start outputting data. This will corrupt any command in progress.

None of the cases you show in Q1, Q2, or Q3 will result in a completed RREG command because the RREG command is interrupted in each case. You must monitor the DRDY signal in RDATAC mode so you know when data is ready to be clocked out, as well as when to avoid sending commands

Regarding Q4: I am not sure what you are asking here, can you provide a diagram like you did for Q1 - Q3?

-Bryan

0 Oba 7 months ago in reply to Bryan Lizon86

TI__Genius 16065 points

Hello Bryan,

Sorry for my very late response.

Regarding Q4, the question is simple.
The case I want to check is when the new concersion data is comming around issuing RDATA like the below figure.

In this case, is the RADATA response data (MSB/LSB) on DOUT valid?
If the data is previous conversion data or new conversion data, it is fine.
But for example if MSB is previous data and LSB is new data, it is a problem.
Is the response data always 16bit valid data, not mixing 8bit old and 8bit new in this case?

Regards,
Oba