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Original question:

ADC12DJ3200: Xillnx IP core tdata does not have the /K28.5/ symbols input after pulling down the sync signal

ADC12QJ1600: cannot receive k28.5

xiaxin
Prodigy 40 points
Part Number: ADC12QJ1600
Other Parts Discussed in Thread: LMK04821

Hello,

  I am using adc12qj1600 ,my sample rates is 1GSPS,and use jmode0,km1=31.but I found that I can't receive k28.5 when the sync is low.the lane data I captured as below.

the adc's register configuration as below

{ 0x0000, 0xB0 }, //#reset registers in the ADCand master pages of the analog bank.750ns self clearing
{ 0x0270, 0 }, //Verify device initialization is completed before continuing by reading INIT_DONE until a 1 is returned.
{ 0x02c1, 0x3F }, //ALM_STATUS
{ 0x02c4, 0xFF }, //FIFO_LANE_ALM
{ 0x002B, 0x15 },
{ 0x002A, 0x02 }, //sysref_lvpecl_en = 1 dclk_lvpecl_en = 0

{ 0x0057, 0x00 }, //TRIGOUT_EN = 0
{ 0x0057, 0x01 }, //TRIGOUT_EN =0 32DIV
{ 0x0057, 0x81 }, //TRIGOUT_EN =1 32DIV

{ 0x0200, 0x00 }, //JESD_EN = 0
{ 0x0061, 0x00 }, //CAL_EN = 0
{ 0x0201, 0x00 }, //JMODE = 0
{ 0x0202, 0x1F }, //K = 32 = KM1 + 1
{ 0x0204, 0x00 }, //SYNC_SEL;offset binary;8B/10B Scrambler disabled
//
{ 0x0048, 0x00 }, //pre-emphasis，if needed
//alarm
{ 0x02c2, 0x02 }, //unmask all the alarm

{ 0x0205, 0x00 }, //test mode if needed
{ 0x0062, 0x01 }, //CAL_CFG0,disable bgos;disable os;disable bg;enable fg
{ 0x0061, 0x01 }, //CAL_EN = 1,enable the calibration state machine

{ 0x0029, 0xA0 },
{ 0x0029, 0xF6 }, //SYSREF_PROC_EN=1,SYSREF_RECV_EN=1,SYSREF_ZOOM=1,SET SYSREF_SEL
{ 0x0200, 0x01 }, //JESD_EN = 1,restart jesd link
{ 0x006c, 0x00 }, //cal_soft_trig to trigger fg
{ 0x006c, 0x01 }, //cal_soft_trig to trigger fg
{ 0x02c1, 0x3F }

could you help me to solve this problem?

  • 0
    TI__Intellectual 1530 points

    Hi Xiaxin,

    Kindly confirm if the SYNC_STATUS bit in the JESD_STATUS register (0x208) is set to '0'. This will indicate that the ADC is seeing the SYNCn as low. If this is set to '1', there may a connection or signaling issue between the FPGA and ADC.

    Alternatively, please try the following sequence:

    1> Set SYNC_SEL in the JCTRL register (0x204) to 0x2. This will override the SYNCn input pin and allow SPI register control of the SYNC

    2> Set the JSYNC_N bit (0x203) to 0x0. This will force the SYNC internally to 0.

    Please check if either of the two options above show the K28.5 characters being received at the FPGA. If not, it is possible that the ADC and FPGA are not using the same JESD lane rate. 

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 40 points

    here are the jesd204b core configuration,the line rates is 8Gbps,also i config the adc's jesd204b modes as jmode0.I think the lane rate at both of FPGA and ADC is the same。

    and the SYNC_STATUS bit in the JESD_STATUS register is also set to 1 according to your advise.I still cannot receice the correct K code.

  • 0 in reply to xiaxin
    TI__Intellectual 1530 points

    Hi,

    If the SYNCn signal is active (low), the SYNC_STATUS bit should read ‘0’, not ‘1’. 

    If the ADC does not see the SYNCn as low, it will not send the K codes  

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 40 points

    Hi Ameet,

    I tried to give the sync signal a fixed 1 or 0,the ADC's syncse port can receive the correct 0 or 1.So I suspect that the serdes rate is still incorrect.i use lmk04821 generating all the clocks.the adc's dclk is 1GHz,sysref is 6.25MHz.the fpga's jesd core clk is 200MHz,qpll clk is 200MHz also,sysref is 6.25MHz.Are those clock frequencies right?

  • 0 in reply to xiaxin
    Prodigy 40 points

    Hi Ameet,

    I have found the problem because I set the sampling clock incorrectly.Now I can recieve K28.5,but at ILAS state,I can't receive K28.0 at the start of frame.the lane data I captrued as below.

    According to my understanding, after the completion of cgs, the ILAS stage should start with K28.0,but I don't know why the data I captured did not start with K28.0.

    Regards,

    Xiaxin