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ADS7046: Need Guidance: Interfacing ADS7046 with STM32H745 for High-Speed Waveform Sampling via SPI

db p
Prodigy 30 points
Part Number: ADS7046

Hello everyone,

I am currently working on the ADS7046 ADC and an STM32H745 microcontroller. However, I am facing challenges regarding accurate waveform sampling via SPI. My objective is to sample a waveform with a frequency of up to 2MHz. Here are the details of my setup and the challenges I am encountering:

Current Setup: I have configured SPI communication between the ADS7046 and STM32H745. Presently, I am utilizing a 16-clock pulse with an SPI clock frequency (SCLK) of 18 MHz.

Challenges: Despite setting up SPI communication, I am experiencing difficulties in accurately sampling the input waveform. Specifically, I am uncertain about the appropriate SCLK frequency and the chip select (CS) on/off timings required to achieve reliable sampling at frequencies up to 1 MHz.

Please suggest the number of clock pulses and the SCLK frequency required to properly sample high-speed waveforms. Additionally, any recommendations regarding hardware requirements, such as RC filter values, would be greatly appreciated.

I have attached some snapshots of the results below.

Here, I have provided some input square and sine pulses from a function generator to the ADC. I have observed that sampling works well at frequencies of 50 kHz and below, such as for 100 Hz, 1 kHz, 5 kHz, 50 kHz, 100 kHz, 150 kHz, 200 kHz, and 250 kHz, up to 500 kHz. However, I am encountering issues with other frequencies, such as 10 kHz, 20 kHz, 25 kHz, 90 kHz, 125 kHz, etc. Could you please assist in identifying the problem?

Thank you for your attention and assistance.

  • 0
    TI__Guru**** 171106 points

    Hi db p,

    Welcome to our e2e forum!  Please review Figure 37 in the ADS7046 datasheet.  The conversion cycle starts with the falling edge of /CS - this is where the analog input is captured (the internal sample and hold capacitor is disconnected from the input).  There is a setup time (see figure 2) before the first falling SCLK edge followed by your 16 SCLKs at 18MHz.  You need the minimum (at least) tACQ time before you drop /CS again.  The longer you wait to apply /CS, the longer you spend in the acquisition phase of the ADC.  Applying /CS with a cycle time of 1uS gets you 1MHz throughput.  By Nyquist, you will be limited to a 500kHz signal @ 1MSPS.

  • 0 in reply to Tom Hendrick
    Prodigy 30 points

    hello tom,

    thanks for your reply . 

    here i attach cs low, high time, sclk cycle 

    as refer page no.5 in datasheet  attach some result of measurement.  

    here I used R=10ohm, C=360pF 

    with above circuit and spi timing i get result i shown above.  but why not smoothly capture. and also not good capture apart from 50khz,100khz,200khz,250khz, 500khz.

  • 0 in reply to db p
    TI__Guru**** 171106 points

    Your tcycle time is 19,34uS, which is a sample rate of ~51.7kHz.  If you look at your 50kHz wave form capture, the first rising edge is sample 11 and the next rising edge is 81 - roughly 70 samples.  That would be a little over 3kHz signal (1/[70*19.34uS]).  

  • 0 in reply to Tom Hendrick
    Prodigy 30 points

    Thanks for your help @TOM.

    I need to capture waveforms ranging from Hz to 1MHz using the ADS7046 ADC. However, I'm a bit unsure about the proper timing parameters and additional filtering required for optimal performance.

    Could anyone please suggest the appropriate timing parameters and any additional RC filter values needed for this task? Specifically, I'm wondering:

    1. How much time cycle (Tcycle) should I give for the ADC to capture waveforms up to 1 MHz? I understand that the sampling frequency (Fs) should be at least twice the maximum frequency of the signal according to the Nyquist theorem, but I'm unsure about the specific timing requirements.

    2. Are there any additional RC filter values I should consider implementing before the ADC? I want to ensure that the captured signals maintain their integrity while suppressing any unwanted noise.

    as referring timing requirement and sclk pulse in datasheet page no.7 and page no. 30 in datasheet of ads7046 single ended i little confuse 

    please suggest me proper sclk pulses and sclk frequency, cs on/ off time Tcycle time for achieve 3msps of capturing upto 1.5mhz waveforms.

  • 0 in reply to db p
    TI__Guru**** 171106 points

    You will need to do the back end math.  Have you reviewed Figure 37?  If you want to sample at 3MHz, the /CS has to toggle at a rate of 1/3000000.  You need at least 15 SCLKS while /CS is low.  You need the minimum setup time for /CS falling to SCLK falling (tsu_CSCK) and the minimum tACQ.  Subtract those two values from the cycle time and divide by 15 to get the minimum SCLK speed that you would need to read out the conversion results.

    Read up on Nyquist and coherent sampling, you may also need an amplifier ahead of the ADS7046.  Feel free to review this video, it may help you understand the sampling process.

    https://www.ti.com/video/5476574757001