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DAC38RF82EVM: In order to have a DAC Clock frequency at 8800 MHz, the evaluation board requires a 1100 MHz frequency reference whereas the DAC reference frequency is 100 MHz

Alain Garot
Prodigy 40 points
Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, , LMK04828, LMK04832

Hello,

I am evaluating DAC38RF82 with the evaluation board (DAC38RF82EVM) and the TSW14J57 pattern generator.

A 100 MHz / +6dBm signal is fed to the input of the LMK (J4 connector).

With the following configuration, all is right, it is possible to get a correct signal at the DAC output.

Now, the aim is to increase the DAC Clock Frequency in order to generate signal at the DAC output from 2000 MHz up to 3600 MHz.

Always with a 100 MHz reference of the system, and using low PLL divider values (for good phase noise achievement), I want to work with a DAC frequency at 8800 MHz (frequency value in the frequency range of the highband VCO).

With the following configuration, the frequency of the signal to be fed to J4 connector on the evaluation board is 1100 MHz ! The purpose is to keep 100 MHz as the frequency reference...

The number of lanes has been increased (from 4 to 8) in order to get a lower Serdes lane rate.

Can someone explain to me why a 1100 MHz signal is required in this case.

Is it really due to the DAC chip itself ?

Or is it due to the evaluation board architecture ?

Thanks for your help !

Alain

  • 0
    TI__Mastermind 18245 points

    Hi Alain,

    Any issue will be caused by the EVM. The DAC itself can operate at 8800MHz through the PLL without issue. As with the other post, please show the same 3 clocking tabs. PLL1, PLL2, and output dividers. 

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 40 points

    Hi Chase,

    Here are the requested information for this setting at 8800 MHz DAC Clock.

    LMK PLL1 configuration:

    LMK PLL2 configuration:

    LMK Clock Outputs:

    DAC Clocking Tab:

    Alain

  • 0 in reply to Alain Garot
    TI__Mastermind 18245 points

    Hi Alain,

    The issue is with the output divider combinations available for this specific mode. The FPGA requires a serdes/10 signal as reference for the LMF821 mode. If the serdes rate is 2.75Gbps then the reference for the fpga for this eval board must be 275MHz.

    The 1100MHz is required as there is no fractional divider options for the LMK04828, only integer. If there was fractional, then you could provide 275MHz and divide the FPGA output by 1 and the DAC output by 2.75 to achieve 100MHz, but that isn't an option. Instead, we have to find a LCM of these two frequencies, 100MHz, 275MHz. This comes out as 1100MHz. The DAC pll reference will be the 1100MHz/11 = 100MHz and the FPGA reference will be the 1100MHz/4=275MHz.

    If you change the FPGA divider value from 16 to 4 then this should work without any other modifications using an 1100MHz input to the J4 connector.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 40 points

    Hello Chase,

     

    When you wrote “The FPGA requires a serdes/10 signal as reference for the LMF821 mode”, do you confirm that this is due to the evaluation board / pattern generator architecture ?

    In our own design using the DAC chip, we will have to define the architecture consequently. Will the use of an external PLL be mandatory ? In order to fed to the FPGA the right clock, to be checked…

      

    Alain

  • +1 in reply to Alain Garot
    TI__Mastermind 18245 points

    Hi Alain,

    Yes, the FPGA reference requirement is driven by the evaluation platform and the FPGA's JESD IP being used. Unfortunately this was created by a third party contract which is no longer with TI so I can't get any of the details about the JESD IP which is being used. Using the LMK PLL2 may or may not be mandatory for certain cases on our EVM/FPGA evaluation solution. I suggest for you to look into choosing an FPGA JESD IP core now to see if you'll need to have any special considerations for clocking. If using a Xilinx FPGA, I would highly suggest to consider the TI-JESD204-IP as TI can provide support for both the DAC and the FPGA core in the event there are any issues with the bringup of your board.

    Another flexibility you can design in is to use the LMK04832 rather than the LMK04828 as the '32 device has integer divider up to 1024 rather than the LMK04828 which has integer divider only up to 32. The register map will be different however there are tools online (TICS-PRO) which can be used to generate new register configuration for that device.

    Thanks, Chase