ADC12DJ5200-SP: C-band, X-band with polarfire

Hello David,

Yes both the ADC12DJ5200RF and DAC39RF10 have JESD interfaces. Do you know what interface speeds the customer is targeting? What would be acceptable?

Thanks,

Eric

Hi Eric

I would like to configure that the maximum band width is 1200MHz and the maximum interface rate is 1500Msps. And the highest center frequency is 9.66GHz. And the lowest center frequency is 5.4 GHz. I would like to use 2 TX channels and 4 RX channels.

Thank you

Hi Eric,

When I was reading the ADC12DJ5200RF datasheet, I could recognize the chip had the two  input channels only.  This means I could not use this chip for my application.

Could you change the AFE7950 firmware to support more lanes per a channel to reduce serdes speed?

For example, in the TX and RX interfaces, if the AFE7950 supports 1500 MPSP  input rate, 12 bits resolution, 8B/10B encoding, 11.25Gbps/lane and 4232 LMFS then I could use the AFE7950 with the FPGA.

Thank you

Hi Byungsoo,

For the LMFS that you are referencing only 2 channels would be enabled. Can you fill out the table below and we can help create a mode for the AFE7950 based on these, if supported?

Regards,

David Chaparro

Hi Chaparro,

Thank you for your reply.

How many TX channels are need. One TX.

The TX sampling rate are 12GSPS.

The TX's interpolation is 8.

How many RX channels are need. One RX.

The RX sampling rate are 3GSPS.

The RX's decimation is 2.

The JESD encoding is JESD204B 8B/10B.

Maximum Lane Rate is 12.5Gbps. It is the maximum data rate of the FPGA.

The maximum serdes lanes are 4 lanes. It can be banded from 1 to 4 lanes.

Use AFE Internal PLL: yes I will use the AFE internal PLL.

Thank you.

Hi David Chaparro,

I am waiting for your reply about my question.

If you need more time, I would appreciate it if you could let me know how much more time you need.

Thank you.

Hi Byungsoo,

Apologies for the late reply. We are creating the customer configuration now, but we have the following question about your mode. Does the JESD encoding have to be 8b10b? When operating at 1500MSPS data rate and 4 lanes for the single channel then the Lane Rate comes out to be 15Gbps, which is higher than the supported rate for your FPGA. If we change to 64b66b encoding we can use the same AFE configuration but the lane rate would now be 12.375Gbps. 

Also, this design would be created for the TSW14J58EVM, but if you have another Xilinx FPGA that you would like this generated for then we can change it. It is important to note that the TI IP only supports the FPGA given on the homepage below.

www.ti.com/.../TI-JESD204-IP

Regards,

David Chaparro 

Hi, David Chaparro,

Thank you very much for your reply.

Unfortunately, we are trying to use the FPGA only supports JESD204B (8B/10B),

so if AFE7950 supports 4232 LMFS, we believe we can implement the functions we want.

resolution : 12
encoding: 8/10b
serdes rate: 11.25 Gbps
LMFS: 4232

Is this possible?

Thank you.

Hi Byungsoo,

Unfortunately the AFE7950 does not support the LMFS 4232 on both the Rx and Tx channels. Additionally with this LMFS the SerDes rate would necessarily fall within your supported range. I will check with our software team on why it is not supported on both. 

While we wait for a response from our software team we can maybe discuss your mode more in order to see if there are any other configurations that could work. What are your requirements on the IBW? Is it possible to work with a slightly lower interface rate? 

Regards,

David Chaparro 

Hi David Chaparro,

Thank you for your reply.

I hope you can find a way to support LMFS 4232 in your software.

The IBW requirement is 1200 MHz.

According to IT's configuration note guide, up to 80% of the interface rate is available in bandwidth,

so we are thinking of an interface rate of 1500 MHz.

Thank you.