ADC12DJ5200-SP: C-band, X-band with polarfire

Hello David,

Yes both the ADC12DJ5200RF and DAC39RF10 have JESD interfaces. Do you know what interface speeds the customer is targeting? What would be acceptable?

Thanks,

Eric

Hi Eric

I would like to configure that the maximum band width is 1200MHz and the maximum interface rate is 1500Msps. And the highest center frequency is 9.66GHz. And the lowest center frequency is 5.4 GHz. I would like to use 2 TX channels and 4 RX channels.

Thank you

Hi Eric,

When I was reading the ADC12DJ5200RF datasheet, I could recognize the chip had the two  input channels only.  This means I could not use this chip for my application.

Could you change the AFE7950 firmware to support more lanes per a channel to reduce serdes speed?

For example, in the TX and RX interfaces, if the AFE7950 supports 1500 MPSP  input rate, 12 bits resolution, 8B/10B encoding, 11.25Gbps/lane and 4232 LMFS then I could use the AFE7950 with the FPGA.

Thank you

Hi Byungsoo,

For the LMFS that you are referencing only 2 channels would be enabled. Can you fill out the table below and we can help create a mode for the AFE7950 based on these, if supported?

Regards,

David Chaparro

Hi Chaparro,

Thank you for your reply.

How many TX channels are need. One TX.

The TX sampling rate are 12GSPS.

The TX's interpolation is 8.

How many RX channels are need. One RX.

The RX sampling rate are 3GSPS.

The RX's decimation is 2.

The JESD encoding is JESD204B 8B/10B.

Maximum Lane Rate is 12.5Gbps. It is the maximum data rate of the FPGA.

The maximum serdes lanes are 4 lanes. It can be banded from 1 to 4 lanes.

Use AFE Internal PLL: yes I will use the AFE internal PLL.

Thank you.

Hi David Chaparro,

I am waiting for your reply about my question.

If you need more time, I would appreciate it if you could let me know how much more time you need.

Thank you.