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ADS127L18: is the DCLK for ADS127L18 a continues clock or burst clock?

Daran Wang
Prodigy 20 points
Part Number: ADS127L18

Can I use DCLK to drive FPGA logic, it needs to be a continuous clock. 

  • 0
    TI__Mastermind 45805 points

    Hi Daran,

    The app engineer is OOO this week and he will come back next Monday (May 13th), please expect a delay on his response, thanks.

    Also, it would be great if you can post all of your questions about the same ADC in the same thread on the forum.

    BR,

    Dale

  • 0 in reply to Dale Li
    TI__Mastermind 46800 points

    Hello Daran,

    Yes, the DCLK, and the FSYNC clock, are continuous clocks whenever the ADC is continuously converting data.  The only time these clocks are idle is when the ADC is used in START/STOP mode.  Figure 5-2 in the datasheet shows the timing relationship, where FSYNC is equal to the data rate, and DCLK depends on the internal register settings.

    Yes, this clock is suitable to connect to an FPGA to transfer data.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 20 points

    Hi Keith

    A follow up question on this:

    If I configure the device use daisy chain, or less of Dout signals, so each Dout will carry multiple of 24bit data for multiple channels. Does the Fsync toggle once for the whole frame, or multiple times per sample. (assume all same sampling rate)

    eg: if I configure the device to use Dout[1:0], then all 8 channels data will be sent out on 2 wires, each dout carries 4 of 24bit data per wire. In this case, the frame sync toggles 4 times or just one time for each sampling interval?

    Thanks

    Daran

  • 0 in reply to Daran Wang
    TI__Mastermind 46800 points

    Hello Daran,

    Fsync always toggles at the data rate, independent of how many channels are multiplexed on a single DOUT line.  In your example, with 4 channels of 24b data on a single DOUT, Fsync will only toggle 1 time.  

    The rising edge of Fsync indicates the beginning of new conversion data.  Both Fsync and DCLK are continuous clocks when the ADC is in continuous conversion mode.

    Regards,
    Keith