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ADC12DJ5200RFEVM: JESD204B Mode 61, A & B link FMC routing

Jeff Stutzman
Prodigy 60 points
Part Number: ADC12DJ5200RFEVM
Other Parts Discussed in Thread: ADC12DJ5200RF

I'm using the ADC12DJ5200RF Evaluation Module and configuring for JESD204B Mode 61 (single channel, 2 lanes, 16x decimation)
5.2 GSps is my sample rate which gives 2.6 GHz sample clock, 6.5 Gbps line rate (8b/10b), 162.5 MHz ref clock.

With my FPGA board, link A lanes (0-3) are routed through the FMC to one transceiver quad and link B lanes (0-3) end up at another quad.
It looks like all JESD modes require two links.  Is there a way I can configure the ADC to use two lanes from Link A only?  DA0 & DA1

I'm currently only able to lock with one lane and the BER test looks good there. (looking into the FPGA IP config with lanes across two transceiver quads as well).

Is there any configuration on the ADC side that could be disabling only one of the two JESD links in Mode 61?

Thanks

  • 0
    TI__Expert 3030 points

    Hello Jeff,

    Unfortunately there is no way to map the B channel lanes to the an A channel output. There are registers to power down the separate channels of A and B which will also shut down the JESD subsystem for that channel. These are default turned off and in this particular mode (61) I would not recommend doing this as it is an interleaved mode. One important note is that on the ADC12DJ5200RF EVM all of the B channel JESD lanes are inverted going to the FMC which is something you will have to account for in your FPGA FW. 

    Additionally, if you would like we do offer custom JESD reference designs to enable fast prototyping on the FPGA side. These designs will be custom for the ADC and mode of operation you choose. If this is something you would be interested in please let me know.

    Best,

    Eric Kleckner

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    Thanks for the reply - I am setting the B Channel lanes to have an inverted polarity at the FPGA.  It sounds like my understanding of the A/B links is correct.  The issue is likely in my FPGA IP.

    Thanks!