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ADC12DJ5200RF: Device clock calculation

Makoto Tsurita
Prodigy 40 points
Part Number: ADC12DJ5200RF

Is the device clock A)4GHz under the following conditions? Or is it B)2GHz?

For example, I want to transmit 12 bits of data per symbol at 4GSps.
The sampling frequency is 4GHz.

A) At this time, 4 tail bits are added to 5 symbols (60 bits) in the transport layer,
Considering 8b/10b conversion, 48Gbps * 64/60 * 1.25 = 64Gbps
When transmitting with 8 lanes, the data rate is 8 Gbps per lane (lane_rate)
When JMODE = 0, it operates in single channel mode and the sampling rate is twice the device clock, so
I calculated that the device clock would be 4GHz.

But, I can think differently.
B) glbl_clk = lane_rate / 40 = 200MHz
device clock = sample_rate / 2 = 2GHz

  • 0
    TI__Expert 3030 points

    Hello Makoto,

    For operation of the ADC in  JMODE 0 the effective sampling rate of the converter is double what you apply at the input as this is an interleaved mode of operation. So in your case you if you sample clock is 2GHz your effective sampling rate will be 4 GHz, but you will only get one channels worth of data.

    Best,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 40 points

    Thank you for your reply.
    In order to have a common understanding, I drew a diagram.

    >So in your case you if you sample clock is 2GHz your effective sampling rate will be 4 GHz, but you will only get one channels worth of data.
    Does "one channels" you are referring to indicate ADC A only?
    If I input 2GHz Device Clock to ADC12DJ5200RF and select JMODE = 0,
    ADC A samples at twice the Device clock and ADC A core operates at 4GSps, right?

  • +1 in reply to Makoto Tsurita
    TI__Expert 3030 points

    Hello Makoto,

    No this understanding is not correct, in single channel mode only INA or INB is active at one given time, the device clock provided to the ADC is 2 GHz and internally both ADC cores will sample the same input on opposite edges of the clock i.e. A samples on the rising edge and B samples on the falling edge.  This results in a single set of interleaved data so the effective sampling frequency of the ADC is 2 times whatever sampling frequency each ADC core is running at.

    So you will only get one channel of data but sampled at twice the speed because internal to the ADC the cores are interleaved.

    Best,

    Eric