ADC12DJ3200: Adjust sampling timing of each ADC with Dual Channel mode

ttd

Part Number: ADC12DJ3200

Tool/software:

Dear Technical Support Team,

Is it possible to use dual channel mode (register 0x201 =3 ) on the ADC12DJ3200 to shift and adjust the sampling timing of the two ADCs between ADC INA and ADC INB?

Q1
Are TADJ_A (0x086) and TADJ_B (0x089) correct for the sampling timing adjustment registers?
If not, please let us know the appropriate register.

Q2
How many CLK cycles or how many seconds can the sampling timing be shifted ?
I didn't find this on the 0x86,0x89 register page

Q3
Is there a setting order specification, before CAL_EN (0x061) or in a different order?
Is there a specified order of settings?

There is a general setup procedure in 8.3 Initialization Set Up,
What steps should be taken to set registers to adjust sampling timing?

...

Best Regards,

ttd

3 months ago

0 Eric Kleckner 3 months ago

TI__Expert 4020 points

Hello,

Yes it is possible to adjust the sampling instance of each adc separately in a dual channel mode.

TADJ_A and TADJ_B are the correct registers, you should change these registers after you complete the initialization setup of the ADC. The step size for the sampling adjusts TAD_COARSE and TAD_FINE can be found in the datasheet, please see the screenshot below.

best,

Eric

0 ttd 3 months ago in reply to Eric Kleckner

Mastermind 7900 points

Hi Eric,

Thank you for your support.

According to "Figure 65. ADC12DJ3200 Clocking Subsystem" on datasheet, TAD_COARSE and TAD_FINE seems to adjust the CLK from CLK＋/CKL-.

TAD_COARSE and TAD_FINE don't have separated register for ADC_A and ADC_B.

After tAD Adjust block, delayed common CLK distribute both ADC_A and ADC_B. It seems that ADC_A and ADC_B same sampling timing this time.

Can TADJ_A and TADJ_B add a additional delay to "tAD Adjusted CLK" for each ADCs separately?

If it is correct, could you inform of me the steps for TADJ_A and TADJ_B.

However, even if it is possible to adjust it with TADJ, I’ｍ concerned about work correctly on the JESD204B side.

Your screenshot seems not to have them and I don't find on datasheet.

Please correct me if my understanding is wrong.

Best Regards,

ttd

0 ttd 2 months ago in reply to ttd

Mastermind 7900 points

Hi Eric,

Do you have any update so far?

TADJ_A and TADJ_B are set factory trimmed value, I guess that I need to read modify write for add or sub (adjusted sampling timing) from current values(current sampling timing with factory trimmed value).

If these are not recommended and steps( xx ps) of TADJ_A and TADJ_B are not disclosed and not user programmable register please let me know.

Best Regards,

ttd

0 Eric Kleckner 2 months ago in reply to ttd

TI__Expert 4020 points

Hello,

I am still looking into this for you if you could give me until the end of the week to get back to you with an answer that would be appreciated.

Thanks,

Eric

0 ttd 2 months ago in reply to Eric Kleckner

Mastermind 7900 points

Hi Eric,

Thank you for your reply.

I'm looking forward to your answer.

Best Regards,

ttd

0 ttd 2 months ago in reply to Eric Kleckner

Mastermind 7900 points

Hi Eric,

Do you have any updates on this?

Best Regards,

ttd

0 Eric Kleckner 2 months ago in reply to ttd

TI__Expert 4020 points

Hello,

Apologies for the continued delay, I am still talking to the design team I will get back to you by the end of the week with a response.

0 Eric Kleckner 2 months ago in reply to Eric Kleckner

TI__Expert 4020 points

Hello,

Apologies for the delay, the TADJ_A and TADJ_B registers have a total delay of 447fs and a average step size of 1.75 fs.

Best,

Eric

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ADC12DJ3200: Adjust sampling timing of each ADC with Dual Channel mode