Tool/software:
Hi,
We are trying to test data through IO pattern checker. If we keep all the data '0' in the register and from the FPGA. there is showing no error in IO test results.
But if we keep data at pattern0 as 'FF' and rest of the pattern value '0' like shown below:
and we keep the 'FF' data value from FPGA at rising edge of frame clock and rest data as '0' as shown below:
So we are expecting IO test result to pass. BUT it is showing all bits high in IO result means there is error in all bits. What could be the reason for this?