OSR_DONE bit not changing

Hi Christoph,

Let me make sure my understanding of what you are attempting to program the device with through the MOSI line is correct. Let me know if there's something specific you want to accomplish that I didn't point out. It would also be useful if you could highlight the critical transfers related to the configuration you are trying to do.

08 01 22: write to the GENERAL_CFG register, clear min, max, and recent statistics, and calibrate offset

08 05 00: write to PIN_CFG register, set all channels as analog inputs

08 07 00: write to the GPIO_CFG register, set all channels as digital inputs. I don't believe this is necessary because if PIN_CFG bits are low, corresponding GPIO_CFG bits are don't cares, so this doesn't need to be set low explicitly. 

08 09 00: write to GPO_DRIVE_CFG register, set all digital outputs as open-drain. Again, don't believe this is necessary if channels are analog inputs instead of GPIOs.

08 03 01: write to the OSR_CFG register, enable oversampling and averaging of 2 samples

08 02 00: write to the DATA_CFG register, normal operation, no channel ID or status flags, SPI mode 0

08 10 00: write to the SEQUENCE_CFG register, sequencing disabled, manual sequencing mode

08 11 00: write to the MANUAL_CH_SEL register, selecting channel 0

10 00 00 & 00 00 00: read SYSTEM_STATUS register, only returns the reserved read as 1 bit

From this, it looks like the averaging setup is being done correctly. Could I see what data you are getting on the SDO pin following the setup, assuming you are giving the device no-op commands? The first conversion must be initiated manually by bringing CS low and providing SCLK. The next conversion(s) will then be controlled with the internal oscillator after bringing CS high. Then, you should expect a 16-bit ADC output value on SDO after bringing CS low again, so you should provide 16 SCLK cycles.

Regards,
Joel 

Hi Joel,

Yes, everything you stated is correct. There are some unnecessary register writes because this is a general init function which is used for other ADS 7038 devices and other configurations. I didn't check for register default values before writing.

"Could I see what data you are getting on the SDO pin following the setup, assuming you are giving the device no-op commands?"

The next data is very similar to the second picture. I do a channel selection followed by a read to the SYSTEM_STATUS register. The returned data from the ADS 7038 looks exactly as above. If you insist I could provide screenshots of the logic analyzer software, but I'm currently working on an other project and would have to setup the environment again.

"The first conversion must be initiated manually by bringing CS low and providing SCLK. The next conversion(s) will then be controlled with the internal oscillator after bringing CS high. Then, you should expect a 16-bit ADC output value on SDO after bringing CS low again, so you should provide 16 SCLK cycles."

This should be achieved by a regular channel selection or do i miss something here?

Hi Christoph,

I have multiple customers with the same concerns that you are experiencing. I'm in the process of running tests to determine if the OSR_DONE bit toggles at all during operation. Allow me until the end of the week to follow up on this.

Regards,
Joel