ADS131E08:IEC 61000-4-2 ESD Ratings? and IEC 61000-4-4 burst Rating?

Hi Daesung,

Welcome to the E2E forum.

The purpose of ESD protection on chips is to protect the device from ESD damage during manufacturing and assembly, but it is not intended to design and protect the finished product when it is powered up.

EMC compliance testing including IEC 61xxx is a system level test. This kind of test is highly related to your PCB board layout design, proper protection design and so on. Definitely you need proper protections for the input, power supplies and interface of your circuit, the protection technique depends on your application, the structure of ADC and so on.

Your PCB stackup is good even though it is not the best design. A solid ground plane is a better approach as I have seen customers failed EMC testing with their split ground layout design and finally passed after they redesigned with a solid ground plane.

We have done an EMC compliance test for a reference design with ADS8686 which is a precision SAR ADC, EMC Compliance Testing for Precision ADC Systems. We will release more application reports for EMC compliance testing and design in the future.

BR,

Dale

Thanks Dale,

so I have additional question,

I understood it you told me about it is better to use a "ground plane" rather than a split ground.

1. it means if using a ground plane, should I use an anti-pad on a PCBA to unuse other layers and go directly to the ground on the 3 layer(ground plane) or 5 layer(ground plane). am I right?

2. Are there any EMC test results for ADS131E08 other than ADS8686?

3. is mandantory digital isolators for SPI Interface's storng EMC conditon?

Hi Daesung,

Please see my answers below.

1. I do not understand what your 'anti-pad on a PCBA' is. A solid ground plane means there is no break in the copper on the inner or top/bottom ground layer, it is just a solid plane. The GND pin of ADC or other components can be directly connected to the solid ground plane through via which provides a short path to the ground plane. A solid ground plane provides some degree of protection against electromagnetic interference (both radiated and received). 

2. Unfortunately, we did not do EMC test for ADS131E08. As I said, this is a system level test and not a standard for chip test, we are doing such a test for some ADCs for specific applications, but the system design guideline to pass EMC test is same for any device.

3. The failure could be caused by any circuit or component in your system including the digital communication between the ADC and your microcontroller. The solution of digital isolation+isolated power supply is very helpful to protect the components from electromagnetic interference and pass the test especially for your strong EMC condition, e.g. 100kHz and 2 or 4kV EFT.

BR,

Dale

Hi Dale ,

Thanks a lot your information. and I have one last question,

PCBA is designed as a 6-layer board, and the TOP and BTM are entirely covered with copper. It is designed as a through-hole board rather than a build-up board, so all grounds are connected.

If you look at my post, the ground plane layers are the 3rd and 5th floors.

Should I direct the via to the 3rd or 5th floor and then strengthen the 3rd and 5th floors with stitching vias?

Currently, the ground of all layer is designed with through-hole vias .

*what I means anti pad of via as here.

Through-hole vias are used rather than build-ups, but the ANTI PAD is set so that the 1st, 2nd, 4th, and 6th floors are not connected to the ground. This allows you to go directly to the ground plane.