Tool/software:
Hello Again TI support Team,
I've been using this ADC in my design for a few months now, and just now noticed an issue that required special attention on signal delay(latency). When I look at the ADC output, I observed approximately 3-4 clocks of additional delay from where I expected the signal to be. In the screen capture below, I expected to see the rising edge of da13_0_porta[13:0] after 3.5clks(2.5clks for DDR to SDR conversion + 1clk of latency) from the rising edge of Usig1 signal. Instead, it is showing much later.
My configuration is CMOS DDR with offset binary enabled(Registers -->0x8F=0x02, 0x92=0x02, and 0x24=0x04).
My set up uses Usig1 signal as trigger which is fed to a FG. The output of said FG is fixed to a delay of zero between these 2 signals and is fed into a Diff Amp which then feeds the square wave into the ADC. I just measure the delay on the output of the ADC and it is not what i expected. Anyways, I'd greately appreciate any feedback that helps me reduce this delay.
Thanks in advance,
Paulino
