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ADS1299: ADS1299: Verifying Test Singal on all channels of ADS1299, waveform is showing peaks on rising and falling edge

Jahan Zeb Gul
Prodigy 10 points
Part Number: ADS1299

Tool/software:

I am in process of programming and controlling ADS1299 using a Microcontroller and for now I am successfully able to read device ID, able to read/write registers and now configured to generate test signal on all channels and plot them on serial port. Below is the screen short of the plot data. I am observing few weried rising/falling edges in test signal. Is it correct ? Currently all the data pins are open and below are my config register settings:

CONFIG1: 96
CONFIG2: D0
CONFIG3: EC
LOFF: 0
CH1SET: 5
CH2SET: 5
CH3SET: 5
CH4SET: 5
CH5SET: 5
CH6SET: 5
CH7SET: 5
CH8SET: 5
BIAS_SENSP: 0

Need opinion if it is correct ? Or any adjustments are required. I want to confirm before proceeding towards biosignals.

Thanks

  • 0
    TI__Guru 60706 points

    Hello Jahan - the test signals look correct at first glance. What exactly is the concern?

    You may want to check how the output codes are converted back to volts. The differential test signal should be centered around mid-scale (0V) with an amplitude described by the register settings. You can refer to our EVM User Guide for an example:

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 10 points

    Many thanks for the reply. I was concerned about the abnormal peaks on the rising and falling edge in the test signal.

    After some testing, I encountered a slightly different problem. When I increase the sampling rate, the test data on the channels starts showing garbage. For example, at 250 samples per second, all channels are correct. However, at 1k samples per second, I find that the last 3 channels show garbage data, as shown below. At the maximum speed of 16k samples per second, all channels display garbage.

    The last 3 plots are channel-6,7,8 and first plot is channel 1-5.

    Similarly when i set 16K samples in config-1, all the plots are showing garbage data:

  • 0 in reply to Jahan Zeb Gul
    TI__Guru 60706 points

    Hi Jahan,

    To me, this appears to be a data capture issue, likely caused by a timing mismatch between when data is written into the output shift register (i.e. nDRDY falling edge) and when the host initiates/completes the data transfer. You must ensure that all data is completely read before the next nDRDY interrupt. The device's default mode (RDATAC) automatically overwrites the newest data into the output shift register.

    Regarding the spikes, this is unexpected, but I'm not sure what would be causing this at the moment. The square wave test signal passes through the PGA and a first-order LPF, so any overshoot/undershoot should be removed. In addition, the sampling rate is so low that I would not expect the ADC output to capture such behavior. Can you plot the raw decimal values and zoom in on just a couple periods?

    Regards,

    Ryan