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DAC38J84EVM: How to set the right clock for this board?

Bowei Yang
Prodigy 30 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04828

Tool/software:

Hi,

I am trying to use the TI_JESD204 IP in vivado to programme my ZCU102 to work with this DAC but it just had no output. The board is tested without problems. I think it's just because I have some trouble with the clocking setting. I 

I tried to follow the clocking set of this one TI_JESD204_IP_KCU105_DAC38J84_841.zip but the I am confused why the external clock frequency is 409.6MHz. And why is the DCLK divider in the tutorial is set to 32? 
I used 156.25MHz external clock and the clock output from CLKout 12 is just 156.25/(Divider I set) MHz which I used as the sys_clock.
Here's the DAC's setting.
 

  • 0
    TI__Mastermind 22660 points

    Hi Bowei,

    I have reviewed this can cannot see anyway that 409.6MHz is related at all here. The DACCLK for that guide shows as 2500MSPS (along with the GUI image showing 2500MSPS), so I am confident the DACCLK is 2.5GSPS, whether that is directly Fin mode on the LMK04828 (simplest) or by providing a lower rate reference and using PLL2 of the LMK04828 to generate a VCO frequency of 2500MHz (which would use VCO0). If you consider this, then the serdes rate for 8411 mode is indeed 1562.5Mbps. The FPGA transceiver reference clock must be valid, usually a frequency which is integer multiple of LMK reference clock (in this case 2500MHz) which lands between 60MHz and 200MHz, depending on the FPGA and transceiver type. Regardless, if we consider the LMKs divider of 32 to be correct as for the MGTREFCLK, then this means the transceiver configuration in the reference design was set for 78.125MHz, which seems like a reasonable value. The second divider is used for FPGA SYSCLK or the application clock on the FPGA. This is the clock rate which should be set for Serdes/80 to achieve full deterministic latency support. It will work at higher SYSCLK frequencies, such as serdes/20, but this will not guarantee a deterministic link bringup latency across power cycles. Also, in your gui picture, the interpolation is set to 1, not 16 - the data rate will stay the same but the DAC sample rate is 16x slower.

    Thanks, Chase