DAC38J84EVM: DAC38J84EVM

Yaron Aronowicz

Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04832, LMK04828

Dear sirs, I have copied the screens as shown on the GUI with the manual settings as we would like to work with. Is it possible to receive from you the corrections for that set up . The best way, as I believe, would be that we will be in touch when the GUI and the Eval., both are in-front of me, than u will be able to guide me best.

DAC3XJ8X_SETUP.docx

over 4 years ago

0 jim s over 4 years ago

TI__Guru* 91947 points

Yaron,

I could get the LMK VCO to be stable with your settings but based on these values, the LMK cannot provide the required clock for the TSW14J56EVM. This would require a decimal divide, which the LMK cannot do. There is a possible work around but you would have to change the 122.88MHz coming from J17 to 134.4MHz. Is this an option for you?

Regards,

Jim

0 Yaron Aronowicz over 4 years ago in reply to jim s

Prodigy 150 points

Hi, Jim , thanks for the fast reply. Could you explaine what is the problem with the Tsw14j56 that I can't provide it the same frequency as I provide the dac, that is lmk's Vco freq. divide by integer number?

I actually decide a bout the 122.88 MHz because this is the same as the one on board vctxo that works just fine.

On my board in which I will send you a question about it as soon as I will understand the issues with the Eval boards, I have a 40MHz vctxo that will supply the ref to the lmk04832.

0 jim s over 4 years ago in reply to Yaron Aronowicz

TI__Guru* 91947 points

Yaron,

The TSW14J56 reference clock needs to be 268.8MHz assuming you are using LMF = 841 and 2x interpolation with the DAC sample rate at 2150.4MHz.

The TSW14J56 reference clock comes from the LMK, which is operating with a VCO = 2457.6MHz. If you divide 268.8 into 2457.6 you get 9.142857.....

The LMK cannot do this divide so the reference clock cannot be set to the correct frequency.

Regards,

Jim

0 Yaron Aronowicz over 4 years ago in reply to jim s

Prodigy 150 points

Ok, got that. I am trying to work with LMF= 222 or 421 , so the TSW14J56 reference clock, would still be 268.8MHz ? Could you please explain the dependency between the Line rate (includes the LMF and the interpolation) and the TSW14J56 reference clock ?

0 jim s over 4 years ago in reply to Yaron Aronowicz

TI__Guru* 91947 points

Yaron,

With LMF = 421, the serdes rate is 5.376Gbps. The FPGA reference clock is serdes rate / 40 = 134.4MHz.

With LMF = 222, the serdes rate is 10.752Gbps. The FPGA reference clock is serdes rate / 40 = 268.8MHz.

In either case, the FPGA reference clock cannot be generated with the LMK VCO at 2457.6MHz.

Regards,

Jim

0 Yaron Aronowicz over 4 years ago in reply to jim s

Prodigy 150 points

DAC3XJ8X_SETUP_134.4.docx

These are the sets for the LMK - DAC as far as I understand it, can U please help me with a better setup so that the PLL at the DAC wil be Locked and the VCO at the LMK will deliver steady frequency without lots o spurs and phase noise ?

0 jim s over 4 years ago in reply to Yaron Aronowicz

TI__Guru* 91947 points

Yaron,

Per the LMK04828 data sheet, the range for VCO1 is 2920-3080MHz. In your attachment you are attempting to set the VCO to 3225.6MHz. This is out of range for this device. Are you thinking of the LMK04832? This board does not have this part installed.

Regards,

Jim