I am doing bring-up of a LM98640QML (LM98640W-MPR) and has problems with getting something on the TXOUTx LVDS pins. The TXCLK and TXFRM behaves as expected. The TXOUTx LVDS are all at constant zero state no matter what I do. I allways starts loading the baseline configuration as specified in the data sheet, i.e. all the 62 registers including all “reserved” but expect the two read only (status and device id). I has noted reserved register address 0x24 shall be loaded with 0x34 – non-zero – is this correct?
Here is what I has tried after the baseline load:
Test 1: Nothing, i.e. baseline config
TXFRM is sample/hold – i.e. no odd/even “signaling” – TXCLK OK, TXOUTx all low
Test 2: Shift to CDS mode. Load:
0x06 ,0x01 ,//Sample & hold
0x00 ,0x05 ,//Main configuration
0x09 ,0x10 //Clock monitor
TXFRM is has odd/even “signaling” – TXCLK OK, TXOUTx all low. Can also see clamp and sample signals on DTM0 and DTM1.
Test 3: LVDS test mode. Load:
0x3D ,0x02 ,//Test & scan control
0x38 ,0x01 ,//Test pattern value MSB
0x39 ,0x55 ,//Test pattern value LSB
0x34 ,0xe0 //Test pattern control
TXFRM is sample/hold – i.e. no odd/even “signaling” – TXCLK OK, TXOUTx all low
Has also tried Test pattern control 0x80, i.e. fixed code – same results
The INCLK is 15MHz. All “analog” seems OK. All supply OK. I have an active CLPIN signal connected
BR
Søren
