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ADC128s102 - split of total supply current (Ia=? Id=?)?

Paul Sorlie
Prodigy 60 points

The subject ADC has separate Analog & Digital supply rails.  The data sheet only lists Total Supply Current, which is the sum of the two.  How can I determine the two currents at my operating point?

  • I'm running slow - closer to 50 kSPS than the reported 1 MSPS.
  • I run V_digital at ~3.3V and V_analog at 5V.
  • I have more resistance between V_a & V_d - about 1500 ohms, not 51.  I have ~10uF on V_d to compensate.
  • Dout has series resistive termination (33 to 100 Ohms), and drives an FPGA pin less than 6 inches away.
  • 25C operation is fine.

What would static I_q be on each?  How would I translate dynamic I_sw for each (A & D) from 1 MSPS to 50kSPS?  I need to know typical supply currents (at a minimum - min / max would be nice) to set the V_ref for the 3.3V V_d.

Thanks!

  • 0
    TI__Intellectual 2905 points

    Hi Paul,

    Let me assume that you are asking for the average currents ID and IA, and not "static". Static currents for this device are: ID=0, and IA=0 (if you stopped the clock with the SC\=HI).

    So, if we are talking average of ID and IA then both of these, to a lage extent, will follow the I=CVf formula. So by scaling the frequency down by a factor of 1Msps/50ksps = 20, you should see the reduction in average ID and IA by a factor of 20 as well.

    Beware that the time averages hide the instantanous nature of these currents: charging and discharging of internal capacitances, shunt current of the internal comparator, etc... So while you may be able to reduce the average output requirements placed on your reference source, you will still need the sufficient decoupling of the VA and VD supplies (caps provide the instantaneous currents).

    Please use the application circuit example in the datasheet as your guide.

    Sincerely,

    tom

  • 0 in reply to Tom Domanski24
    Prodigy 60 points

    Wow, thanks for the quick response Tom!  Yes, average I_digital & I_analog.  I will use the total current at shutdown for a y-intercept of a current formula:  I_total = I_shutdown_total + (F_oper / F_AppNote) * I_normal_total.  I can also use I=CVf to adjust I_digital for 3.3V operation as opposed to the datasheet's 5V.

    I still need to know the split (or ratio) between I_digital & I_analog so I can bias my Vref creating V_digital.  It's hard for me to measure & my sample size would be small.  Total is 3.1mA max.  Is that 1mA analog & 2.1mA digital?  3mA analog & 0.1mA digital?

    I always try to 'leverage' the app circuit example, but here the FPGA interface was not 5V-tolerant in all cases. Using a zener near it's knee for ~3.5V seems like the best low-power way to protect the FPGA. Not a low R_out 3.3V supply, but also not wasting 150mW to power a 1mW part.  A simple voltage divider fails if I_digital ever goes too low.  In my previous design using this ADC, increasing resistance of the isolation resistor from 51 Ohms & adding 'local battery' of bulk caps on V_digital worked fine.

    Thanks again for quick info, & I look forward to those average currents!

    Paul

  • 0 in reply to Paul Sorlie
    TI__Intellectual 2905 points

    Hi Paul,

    I need a bit of time to dig up the data you are asking for.

    Post to this thread again tomorrow, if you don't see anything from me before then.

    Cheers!

     

    tom

  • 0 in reply to Tom Domanski24
    Prodigy 60 points

    Tom,

    Will do, thanks for digging in!

    Paul

  • 0 in reply to Paul Sorlie
    TI__Intellectual 2905 points

    Hi Paul,

    Below is a summary of results of one chracterization lot. Sample size is only 20, but it trurns out this sample is representative of our production material.

    Supply A - is the RMS IA current

    Supply D - is the RMS ID current

    FIN - is the frequency of the input sinusoid

    CLK - frequency of the SPI clock

    CHAN - input channel selected

    DCYCLE, DUTY% - duty cycle of the SPI clock

    Note that the test conditions are similar to you application: VA = 5V, VD = 3V

    The device is operated in continuous conversion mode (CS\ is held low, and device continuously converts and sends out data frames)

    The loading on the DOUT is about 10pF

    Bottom line: the split is about ID=40uA / IA=1.3mA

    Temp

    Test Id

    TEST

    SupplyA

    SupplyD

    CHANNEL

    CLK

    FIN

    DCYCLE

    DUTY %

    units

    OBS

    AVG

    MAX

    MIN

    SIGMA

    -45

    227

    Supply A

    5.00

    3.00

    1

    8.00MHZ

    40K

    0.50

    50

    uA

    20

    1261.75

    1347.81

    1219.06

    31.2221

    -45

    228

    Supply D

    5.00

    3.00

    1

    8.00MHZ

    40K

    0.50

    50

    uA

    20

    41.5063

    43.3125

    40.6875

    0.571349

    25

    227

    Supply A

    5.00

    3.00

    1

    8.00MHZ

    40K

    0.50

    50

    uA

    20

    1193.8

    1272.81

    1154.38

    27.7151

    25

    228

    Supply D

    5.00

    3.00

    1

    8.00MHZ

    40K

    0.50

    50

    uA

    20

    41.6688

    43.125

    40.9375

    0.576079

    110

    227

    Supply A

    5.00

    3.00

    1

    8.00MHZ

    40K

    0.50

    50

    uA

    20

    1112.31

    1185.94

    1071.25

    28.0258

    110

    228

    Supply D

    5.00

    3.00

    1

    8.00MHZ

    40K

    0.50

    50

    uA

    20

    42.5562

    43.6875

    41.8125

    0.506496

     

    Sincerely,

     

    tom

  • 0 in reply to Tom Domanski24
    TI__Intellectual 2905 points

    Paul,

    Can you see all 16 columens in the table above?

    tom

  • 0 in reply to Tom Domanski24
    Prodigy 60 points

    Hey Tom.  Yes, I can see all the columns.  This is exactly what we needed!  Down to the C_load.  I am delighted, and so thankful for the quick response.  E2E will be my first stop for info from now on!!!

    Paul

  • 0 in reply to Paul Sorlie
    TI__Intellectual 2905 points

    Hi Paul,

    I am glad we were able to help you.

    Take care.

    Sincerely,

    tom