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I noticed a post on this forum about some timing issues with the THS1207. I have been dealing with some very odd behaviour of a THS1206 in single conversion two channel per conversion mode at about 500kS/s. Using FPGA to generate CS1, CS0 and RD I found that only certain patterns of CS1,CS0 and RD would result in consistent sampling from the internal FIFO and proper generation of subsequent Data_available pulses. I wonder if anyone from TI would be willing to comment on this issue? The timing that I had to generate to get the device to work is definitely not described in the data sheet.