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DAC8411 - Timing Requirements for Serial Write Operation

Hirotaka Matsumoto
Guru 27585 points
Other Parts Discussed in Thread: DAC8411

Hello,

I'd like to confirm Timing Requirements for Serial Write Operation.
Test conditions show as followings on the data sheet(on Page7);

<Timing Requirements(correct values)>
In case of AVdd = 3.3V,
1. SCLK cycle = min 50ns
2. SCLK high time = min 25ns
3. SCLK low time = min 25ns

<Question>
If input SCLK pulses(cycle, high time and low time) are shorter as like -Example conditions- than above values , 
does the DAC8411 output false values, or not at all?
If you know, could you tell us?

-Example conditions-
SCLK cycle = 45ns
SCLK high time, low time = 22ns

Then, we promise that we never use under <Example conditions>.
We know this is illegal direction.

Hirorotaka Matsumoto

  • 0
    TI__Genius 10615 points

    Hello Matsumoto-san,

     

    The DAC8411 SCLK is guaranteed to work at a minimum of 50ns SCLK cycle time with AVDD = 3.3V. There is small headroom, but due to process variations any smaller cycle time cannot be guaranteed to work as expected. We cannot predict if the part will work correctly, latch in the wrong value or simply disregard the command.

     

    Regards,

  • 0 in reply to Eugenio Mejia
    Guru 27585 points

    Hello Eugenio San,

    Thank you for your reply and your kindness.
    We understood your saying completely.

    Kind regards,

    Hirtotaka Matsumoto