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Can DAC8805 interface with TMS320F28335?

qian wang
Prodigy 60 points
Other Parts Discussed in Thread: TMS320F28335, DAC8805, ADS8556

Hello,

I'm working on a servo project, and want to interface TMS320F28335 with DAC8805 via parallel interface, and I studied the timing requirements of these two parts on datasheets carefully, but there is still one point confusing me:

According to 28335's datasheet, the WE signal of XINTF goes low before data is valid, as shown in the picture below:

while on DAC8805's timing diagram, it seems that the WE signal goes low the same time as data becomes valid, as shown below:

Can these two parts interface with each other via parallel interface?

Thanks very much in advance.

qian.w

  • 0
    TI__Genius 10615 points

    Hi Qian,

    qian wang said:
    Can these two parts interface with each other via parallel interface?

    Yes. I can verify for you that the two parts can interface with each other via parallel interface.

    qian wang said:
    while on DAC8805's timing diagram, it seems that the WE signal goes low the same time as data becomes valid

    Yes. This is correct, but it is only after 10 ns (tDS) of setup time that the data becomes valid.

    Just to clarify, the correlations you are using between the TMS and DAC timing diagrams are as follows:

    • XA      to DAC_A0/1
    • /XWE to DAC_/WR
    • XD     to DAC_DATA

    I believe your first image is Figure 6 - 24 in the TMS320F28335 datasheet. The timing spec td(XWEL-XD) is 1ns. Meaning that the data is valid after 1ns of the falling edge of /XWE.

    The key things to notice here are:

    • The Active time for /XWE must be >= 11ns. This fulfils the 1ns requirement of the TMS, as well as the 10ns setup time of the DAC. (The hold time of the DAC is 0ns).
    • The Lead time for XA must be >= 10ns. This fulfils the DAC tAS timing requirement.

    I have one question. How do you intend to control LDAC? The rising edge of LDAC is what will ultimately update the DAC output register. There are a few options depending on how you would like to control it. Please take a look at Table 3 in the DAC8805 datasheet for some options.

    Let me know if you need any more assistance.

  • 0 in reply to Eugenio Mejia
    Prodigy 60 points

    Hi Eugenio,

    Thanks very much for your reply:)

    Yes, the first image I posted is Figure 6 - 24 in the TMS320F28335 datasheet. And I connected TMS and DAC8805 as follows:

    • XA0/1      to DAC_A0/1
    • /XWE      to DAC_/WR
    • XD          to DAC_DATA
    • GPIO     to DAC_LOAD_DAC

    I plan to use a GPIO as LOAD_DAC signal, and use seperate WR and LOAD_DAC pulses as shown in figue1 in DAC8805 datasheet.

    tLWD may be fulfilled by proper trail setting of TMS XINTF, and  tLDAC can be fulfilled by inserting two NOP insturctions

    between driving the GPIO high and low, considering the 6.67ns clock time of TMS.

    I wonder what would happen if the /XWE and LOAD_DAC are tied together, it seems if tied together, the data should be setup before the falling edge of /XWE, then the timing requirements could not be fulfilled. Is that correct?

    Qian Wang

     

  • 0 in reply to qian wang
    TI__Genius 10615 points

    I'm glad I was able to assist you.

    Answering your questions:

    qian wang said:
    between driving the GPIO high and low, considering the 6.67ns clock time of TMS.

    I urge you to check Section 6.9 in the TMS320F28335 datasheet. Here you can find the maximum toggling speed for the GPIOs. I am not an MCU speciallist, so if you are still unsure about the max speed, it might be a better idea to post in the MCU forum.

    From what I was abled to read, it seems that the min period for the TMS is 40ns. This is usually because it takes a few clock cycles for the GPIO update signal to propagate through the device.

    qian wang said:
    I wonder what would happen if the /XWE and LOAD_DAC are tied together, it seems if tied together, the data should be setup before the falling edge of /XWE, then the timing requirements could not be fulfilled. Is that correct?

    Yes. They can be tied together. There will be no problems. The DAC is designed to be able to operate under this condition. It is outlined in Table 3 of the DAC8805 datasheet. The timing requirements for /XWE in my previous reply would still apply, there are no new timing requirements. The data will be valid on the rising edge of LDAC.

    I hope this provides the functionality you are looking for.

    Do you think that you share some of the details of the application? Why do you have to drive the parallel interface as fast as possible? We are always interested in how our customers use our devices in order to better define devices in the future. If you don't feel comfortable sharing information like this in a public forum, would it be okay to contact you to your E2E registered email?

    If you have any other questions about this or any other device please let me know :)

  • 0 in reply to Eugenio Mejia
    Prodigy 60 points

    Eugenio Mejia said:

    I urge you to check Section 6.9 in the TMS320F28335 datasheet. Here you can find the maximum toggling speed for the GPIOs. I am not an MCU speciallist, so if you are still unsure about the max speed, it might be a better idea to post in the MCU forum.

    From what I was abled to read, it seems that the min period for the TMS is 40ns. This is usually because it takes a few clock cycles for the GPIO update signal to propagate through the device.


    Yes, I think you are right, I forgot about the toggling speed of the GPIO. so the minimum LDAC width should be 40ns.

    Eugenio Mejia said:

    Do you think that you share some of the details of the application? Why do you have to drive the parallel interface as fast as possible? We are always interested in how our customers use our devices in order to better define devices in the future. If you don't feel comfortable sharing information like this in a public forum, would it be okay to contact you to your E2E registered email?

    If you have any other questions about this or any other device please let me know :)

    I can talk about my project without too much details :) And also you can feel free to contact me through the E2E email.

    Currently I'm working on a special digital servo control system, the bandwidth of this system is quite wide (compared to conventional servo systems).

    I plan to use a cycle time of 5uS or less for the current loop calculation, and a power stage working in linear operation mode instead of PWM mode to achieve wide bandwidth (at the cost of low power efficiency).

    I choose DAC8805 to drive the power stage, and DAC8805 has two good features for this application: it can reset to mid-scale, and it it a multiplying DAC.

    Reset to mid-scale can prevent unintended motion of the motor on system powering-up, and multiplying feature gives me more flexibility in system design.

    From real-time control point of view, the delay from acquiring the feedback information to updating the DAC should be minimized, so I choose parallel interface.

    I hope this information is useful to you.

    Qian

  • 0 in reply to Eugenio Mejia
    Prodigy 60 points

    Hi Eugenio,

    I have another question for the same project now, I connected ADS8556 on the same bus as DAC8805, so the schematic is like this:

    I wonder whether there will be any conflict between ADC and DAC in the D0:D14 signals. If the ADC can put the D0:D15 to high-impedance mode when CS is high, then there seems to be no problem,

    I looked through ADS8556's datasheet but didn't find explicit indication that the data signals will be high-impedance when CS is high, I only found that in the table on page 8 there

    are the high-impedance characteristics of the digital outputs:

    BTW, I didn't put any buffer registers on the data bus,  can you tell me whether  ADS8556 and DAC8805 can share the data bus without conflict?  Thanks very much.

     

  • 0 in reply to qian wang
    TI__Genius 10615 points

    Hi Qian,

    qian wang said:
    can you tell me whether  ADS8556 and DAC8805 can share the data bus without conflict?

    Yes, you will be able to drive them both without problem.

    When you want to communicate with the ADS, you will need to do the following:

    • ADS: /CS LOW
    • DAC: W/R HIGH, LDAC LOW

    When you want to communicate with the DAC, you will need to the following:

    • ADS: /CS HIGH
    • DAC: Whichever combination you prefer.

    Hopefully this answers your questions. Let me know if you still have some questions.

  • 0 in reply to Eugenio Mejia
    Prodigy 60 points

    Hi Eugenio,

    Thanks very much for your timely reply:)