Dual DAC37J84 Eval Cards

Jon Reyland

Other Parts Discussed in Thread: DAC37J84, LMK04828, DAC38J84, DAC38J84EVM

Hello,

My JESD Verilog program has a JESD204 phy layer driver for each DAC37J84 Eval card, those also work well.

The problem is synchronizing SysRef to each of the two DACs. I generated a 800 nsec. pulse, and sent it to pin 6 SYNC input of each LMK04848 (I may have that part number wrong but you know what I mean) clock cleaner chip (one on each eval card), However I can't figure out what to set the LMK SysRef Mux and Sync modes to. Would you please recomend the LMK setups I need? I really appreciate your help

Thanks,

John Reyland

over 9 years ago

0 Kang Hsia over 9 years ago

TI__Guru* 78124 points

Hi Jon,

To achieve synchronization of the sysref signal of two separate LMK04828 on two EVMs, we have to use the 0 delay feature of the LMK04828 (see figure 18 and figure 19 of the LMK datasheet). By feeding a common reference that is the same frequency as the sysref signal to both LMKs, the PLL1/PLL2 would ensure the delay throughout the chip are the same through negative feedback. We have a setup here that I can take some snap shots for you to reference. If you want, please also let me know how you are setting up your DAC device (i.e. LMF settings, interpolation, etc) and I can try it here in the lab as well.

The clocking expert in the clock forum can give you more advise on synchronizing multiple LMKs in direct buffer/divider mode. My understanding is that the internal clock used to capture the SYNC pulse is a divided down version of the input clock. Everytime a division is made, the divided down clock may have phase uncertainty. (i.e. /2 creates 0 and 180 degrees of phase possibility, while /4 creates 0, 90, 180, and 270 degrees of phase possibility). If there are two LMK devices capturing the same sync, the issue may not be the sync but the clock that is capturing the sync (or the internal delay, etc). This is the reason why in 0delay mode, all of the divider settings are set to /1 in the feedback path to avoid phase ambiguity.

-Kang

0 John Reyland62 over 9 years ago in reply to Kang Hsia

Intellectual 375 points

Hi Kang,

Thanks for the helpful comments. I am attaching a MSWord document that shows all the setups for both of the DAC37J84 eval cards I am trying to synchronize. Referring to the eval card schematic and also to the LMK04828 data sheet, Figure 11, here is some additional info about my current setup:

1. CLKin0 is not connected
2. CLKin1/Fin/FBCLKin on both eval cards is connected to a stable sampling clk source (983.04 MHz)
3. OSCin is not connected (Y1 on eval card is powered off)

Would you please explain what you mean by "feeding a common reference that is the same frequency as the sysref signal to both LMKs'? How do I figure out the reference frequency and where is it connected please?

Do you have cascaded or nested 0-delay mode setup?

Thanks again for your advice, I really appreciate it.

John Reyland

0 Kang Hsia over 9 years ago in reply to John Reyland62

TI__Guru* 78124 points

Hi John,

I don't see an attachment, could you attach again?

Also, I will try to capture some screen shots for you so you can understand my setup.

0 John Reyland62 over 9 years ago in reply to Kang Hsia

Intellectual 375 points

Hi Kang,

Did you receive my MSWord document with all the eval card setups I am using please?

Would you please help me with the question about generating synchronized SysRef on each of two DAC eval cards. Here is my original question:

I have two DAC37J84 Eval cards connected to two FMC connectors on a Xilinx VC707 FPGA Eval card. Using the TI DAC setup GUI, I setup both eval cards with external clock and drove both with a 983.04 MHz clock, no problem. My JESD Verilog program has a JESD204 phy layer driver for each DAC37J84 Eval card, those also work well.

Here is some additional information:

Referring to the eval card schematic and also to the LMK04828 data sheet, Figure 11, here is some additional info about my current setup:

1. CLKin0 is not connected
2. CLKin1/Fin/FBCLKin on both eval cards is connected to a stable sampling clk source (983.04 MHz)
3. OSCin is not connected (Y1 on eval card is powered off)

Would you please explain what you mean by "feeding a common reference that is the same frequency as the sysref signal to both LMKs'? How do I figure out the reference frequency and where is it connected please?

Do you have cascaded or nested 0-delay mode setup?

Thanks, John Reyland

0 Kang Hsia over 9 years ago in reply to John Reyland62

TI__Guru* 78124 points

Hi John,

I did not see the original MS word document. Could you re-attach the link? I will also private message you to see if you can send it to me directly via email.

-Kang

0 Kang Hsia over 9 years ago in reply to John Reyland62

TI__Guru* 78124 points

Hi John,

Attached is the powerpoint showing my setup and a document about SYSREF. I am in the process of creating app note/TI design related to your setup. I think these will answer your question regarding nested 0-delay mode setup.

-Kang

DAC38J84 EVM LMK04828 Nested 0 delay Setup.pptx DAC38J84 SYSREF Configuration1-8-2016.pdf

0 John Reyland62 over 9 years ago in reply to Kang Hsia

Intellectual 375 points

Hi Kang,

Thanks your PP presentation entitled "DAC38J84 EVM LMK04828 Dual Nested 0 Delay PLL Setting".

One question please, is K on page 3 of your presentation the same as K on the top right of DAC GUI page "DAC3XJ8X - JESD Block"? Also, if K = 10 = number of octets per frame then how come Table 9 of the DAC37J84 data sheet shows 8 octets per frame for the LMF=442 mode?

Thanks, John Reyland

0 Kang Hsia over 9 years ago in reply to John Reyland62

TI__Guru* 78124 points

John,

Glad that it helps.

The number of octets per frame in Table 9 is abbreviated as "F"

"K" is the number of frames per multi-frame. This number has to match on your JESD204B TX (FPGA).

-Kang

0 Jon Reyland over 9 years ago in reply to Kang Hsia

Intellectual 280 points

Hi Kang,
Seems like page 2 of your “DAC38J84 EVM LMK04828 Dual Nested 0 Delay PLL Setting” presentation has F and K definitions swapped. What do you think?
In my case LMF = 841 and JESD lane rate is 9830.4 MHz. If K = 20 then please verify that my SysRef frequency is 9830.4/(10*20) = 49.152 MHz.
I really appreciate your help. I’m eager to try out your dual eval card setup.
Thanks,
John Reyland

0 Kang Hsia over 9 years ago in reply to Jon Reyland

TI__Guru* 78124 points

Hi John,

I made a mistake on page 2 of ppt. I have updated it. The definition for K and F are swapped. I am re-attaching the updated ppt for future reference

What is your input data rate per channel (MSPS) and interpolation rate for 841 mode? I want to confirm your lane rate calculation first.

In your equation, you did not account for F = 4. The max SYSREF frequency is 9830.4/10/4/20, which is 12.288MHz.

-Kang

4466.DAC38J84 EVM LMK04828 Nested 0 delay Setup.pptx

0 Jon Reyland over 9 years ago in reply to Jon Reyland

Intellectual 280 points

Hi Kang,

My parameters are:

DAC Data Input Rate = 983.04 MSPS
Number of SERDES Lanes = 8
Interpolation = 1
DAC Output Rate = 983.04 MSPS
FPGA Clock = 245.76 MHz
JESD Mode = LMFS = 8411
SERDES Line Rate = 9830.4 Mbps

From the GUI page labeled "DAC3XJ8X controls -> JESD Block" under the heading "Configuration for all lanes" I have
L = 8, M = 4, F = 1, K = 20, S = 1

If LMF = 8411 then doesn't F = 1? If so, is there some other error in SysRef frequency = 9830.4/(10*20) = 49.152 MHz ?

Thanks for your interest and advice!

John Reyland

0 Kang Hsia over 9 years ago in reply to Jon Reyland

TI__Guru* 78124 points

Hi John

sorry. Yes, I made another mistake. F is 1 as you mentioned, I was reading too fast and used M instead.

SYSREF = 49.152MHz max. You can probably set up the LMK using the default start-up page using button #1. Once programmed, configure the dual loop zero delay setting accordingly.

0 Jon Reyland over 9 years ago in reply to Kang Hsia

Intellectual 280 points

Hi Kang,

Going by your presentation, I think I got all the LMK04828 PLL0 and PLL1 dividers to work. However, the DAC GUI changes my setups when I change screens. Why does it do that? Can I make the settings stay where I want them please?

Thanks,
John

0 Kang Hsia over 9 years ago in reply to Jon Reyland

TI__Guru* 78124 points

Hi John,

Once you have a preferred configuration, use the save configuration feature under the Low Level View of the DAC GUI. You can save the LMK + DAC settings into one configuration text file and reload later.

If you need to configure two DAC EVMs, you will then need to unplug the USB port of one EVM, and connect to the other EVM and perform loading of the configuration file. The DAC GUI only recognize one DAC EVM at a time.

-Kang

0 Jon Reyland over 9 years ago in reply to Kang Hsia

Intellectual 280 points

Hi Kang,

I setup my DAC GUI V1.1 carefully, read the config from the DAC eval card to make sure it is correct and then save config. After reading config back, the GUI has changed my PLL setting. I just can't get it to work the way you suggested. Not a huge problem because by this time I have memorized required settings!

Thanks again for the PP slides. They are a great help. One suggestion is to provide more details on page 3. For example, what is LMFC and why do we need to know it here.

Thanks,
John Reyland

0 Kang Hsia over 9 years ago in reply to Jon Reyland

TI__Guru* 78124 points

Hi John,

There may be some issue with the register save function. I would recommend saving it again to a different file and reload it to the EVM to see if the setting matches. Once it matches, you may use the config file to load another EVM.

Noted on the LMFC description. We have some training under the following link:
www.ti.com/.../high-speed-adc-greater-10msps-jesd204b.page

I am also in the process of compiling this into a TI Design Note with more descriptions.

By the way, were you able to get delayed matched SYSREF on both EVMs? I just want to make sure the same setup can be duplicated.
Thanks

-Kang

0 Jon Reyland over 9 years ago in reply to Kang Hsia

Intellectual 280 points

Hi Kang,

Thanks for the link to the JESD slides, I read them.

I am using one Virtex 7 eval card to drive the two DAC37J84 eval. cards. The Virtex 7 eval card has two complete high density FMC connectors. As you know, each DAC eval card has an FPGA clock feedback that comes from the LMC04828 and is wired to the FMC connector. In my case this is 245.76 MHz. Using your DAC setup scheme, I was able to output the two FPGA clock signals and check that they are locked together. So this implies that the sampling clock and SysRef clocks are also in sync?

Now, sine waves output from the two DAC eval cards are still not locked together. Am I missing something?

Thanks,

John Reyland

0 Jon Reyland over 9 years ago in reply to Jon Reyland

Intellectual 280 points

Hi Kang,

Referring again to your power point "DAC38J84 EVM LMK04828 Dual Nested 0 Delay PLL Setting", with all the settings you describe and the 61.44 MHz input (I have about 1.5 VPP, 0 VDC sine wave on the CLKin1 LMK04828 CMOS input) does the DAC eval card PL1 or PLL2 locked LED come on please? Mine does not and there are cycle slips between the external and internal SysRefs.

Thanks,
John

0 Kang Hsia over 9 years ago in reply to Jon Reyland

TI__Guru* 78124 points

Hi John,

I have created a Nested 0 delay PLL setting under your condition at 983.04MHz, 1x, 841 mode. The SYSREF generated is at 12.288MHz (which is 49.152MHz/N = 4). Under this condition, you should see both PLL1 and PLL2 locked LED lit up. Be sure to apply a 12.288MHz clock to the J17 connector.

I have tested the setup over here in the lab with our TSW14J56 EVM and I was able to get the correct output. Try this out and see if you can duplicate your setup.

Note: for some reason, if I apply 49.152MHz (SYSREF divider = 60) to the J17 pin, I cannot get the PLL1 status light to lit up. Once I set the SYSREF to 12.288MHz (SYSREF divider = 240) and J17 = 12.288MHz, the PLL1 LED lit up. You may want to check with the clocking forum for exact LMK04828 set up based on your requirement. This should not impact the LMFC alignment and SYSREF alignment on both LMKs.

Regarding the Xilinx setup, you may want to check with your local Xilinx support. I know we are still working on Altera platform. I believe the key is to get the triggering system working on the FPGA. We have two TSW14J56 EVMs, one in master mode and one in slave mode. The master will trigger the slave upon sending the data, and both FPGA EVM will delay the sample one LMFC afterward to ensure aligned data are send to the two DAC EVMs. Since the SYSREF going to the FPGA are aligned, the LMFC of both FPGA EVMs are aligned as well.

-Kang

0_delay841_983p04MHz_1x_SYSREF_12p288MHz.cfg

0 Jon Reyland over 9 years ago in reply to Kang Hsia

Intellectual 280 points

Hi Kang,

The work you did to understand my DAC setup really helped. I now have both DAC cards fully synched. Put of my problem was that I think there is a 40MHz limit on the LMK04828 ClkIn inputs So that may be why your 12.288 MHz SysRef works and my 49 Mhz did not. The limit is probably in the data sheet somewhere.

I am using a Xilinx VC707 Virtex 7 card that has two fully functional JESD interfaces on it, so my JESD sync-up is a little simpler. I have to use ribbon cables to connect the DAC eval cards because the FMC connectors are right next to each other.

Thanks again for your help!!!
John

0 Kang Hsia over 9 years ago in reply to Jon Reyland

TI__Guru* 78124 points

thanks for the feedback. Glad to hear that your set up is working.

0 Kang Hsia over 9 years ago in reply to Kang Hsia

TI__Guru* 78124 points

For future reference, here is a preview to the TI Design note related to multiple DAC3xJ8x device synchronization over JESD204B link:

0714.Published_TIDUBH1_TIDA-00996.pdf

0 user3549179 over 9 years ago in reply to Kang Hsia

Prodigy 60 points

Hello Kang Hsia ! I recently bought a DAC38J84evm and a TSW14J56evm , and want to test my own JESD204B program on it. After see this post I harvest a lot . Where can I download the document whitch you talking about and including 7.3.1.2.5 JESD204B Pattern Test and 8.3 Initialization Setup ? I think it is useful for my test , Thanks a lot!